John Bagshaw
Toronto,ON
Summary
Innovative SoC/FPGA Systems Engineer with 6+ years in ASIC/FPGA design and verification, specializing in digital signal processing for 5G, GNSS systems, satellites, AI/ML, IoT and medical diagnostics applications. Skilled in low-power, high-reliability solutions with a record of delivering successful projects in fast-paced, innovative environments. Demonstrated expertise in AI models (Linear Regression, Support Vector Regression, Random Forest, Gradient Boosting, and K-Nearest Neighbors) and high-speed communication protocols (PCIe, Ethernet, Aurora, JESD204, I2C, SPI, and UART). Proven ability in delivering complex FPGA designs from conception to deployment and experienced in partial reconfiguration and high-level synthesis (HLS) with aa solid foundation in embedded Linux, Verilog, C++, and Python. Eager to apply my expertise to drive innovations in non-invasive diagnostic technologies.
Overview
7
7
years of professional experience
5
5
Certification
Work History
Hardware/Software Design Team Lead
York University
12.2019 - Current
- Modified existing software to correct errors and adapt to newly implemented hardware or upgraded interfaces.
- Monitored team performance and provided constructive feedback to increase productivity and maintain quality standards.
- Devised and implemented processes and procedures to streamline operations.
- Utilized High Level Synthesis (HLS) FPGA design approach and reduced design time by 25 percent including multiple design verification layers for proof-of-concept.
- Integrated custom IP blocks in previously developed systems using electronic test equipment.
- Performed hardware-in-the-loop testing and debugging on custom- designed hardware according to customer's specification.
- Developed design documentation and generated technical reports.
- Performed test coverage analysis for continuous improvement and identified opportunities for innovation within design.
- Modified existing software to correct errors, and adapt to newly implemented hardware or upgraded interfaces.
- Integrated object-oriented design and development techniques into projects to support usability goals.
- Analyzed code and corrected errors to optimize output.
- Assessed code during testing stage to determine potential glitches and bugs.
- Established clear system performance standards and wrote specifications.
- Monitored equipment function to verify conformance with specifications.
- Conferred with project managers and other stakeholders to fully understand software design specifications and plan optimal development approaches.
- Coordinated system installations, testing, and code corrections.
- Implemented unit and integration testing protocols to consistently deliver high-quality, functional features with minimal defects.
SoC/FPGA Project Lead
York University
08.2019 - Current
- Led FPGA-based projects for diverse applications, including GPS receivers and DSP modules, from inception to deployment
- Developed and optimized embedded firmware for high-reliability environments, including medical applications
- Implemented machine learning algorithms to enhance system performance and predictive accuracy in traffic control systems
- Achieved improvements in design process and performance metrics, documented extensively for transparency and future reference.
- Spearheaded and performed FPGA partitioning, synthesis, simulation, emulation, FPGA prototyping, silicon bring-up and debug.
- Conducted design simulations using prototype test benches and performed in-depth RTL verification of hardware prototypes for complex designs.
- Spearheaded design and development of digital RF technology solutions for satellite systems, aligning with needs of market leader in low-power GNSS chipsets.
- Developed complex logic for large FPGAs in high-reliability environments including medical environments.
- Spearheaded project meetings with team members to discuss ongoing, planned, and recently completed projects.
- Selected design components including FPGA devices, memories, and power supplies.
- Utilized high-speed (10+ Gb/s) serial interfaces and peripheral interfaces such as SPI, PCIe, Ethernet, Aurora, JESD204 and I2C.
- Analyzed traffic volume data using AI/ML models such as Linear Regression, Support Vector Regression, Random Forest, Gradient Boosting and K-Nearest Neighbors to enhance predictive accuracy.
- Developed architectural design of FPGA systems that interface to external interfaces and processors including automated design flows using TCL scripting.
- Demonstrated deep understanding of 5G digital signal processing and FPGA design by developing comprehensive HLS C/C++ and Verilog/VHDL codes, encompassing signal acquisition, channel estimation, beam-forming weight calculation, and signal combination.
- Developed and implemented verification test plans for custom IP blocks and FPGA subsystems including benchmark constraints and latency analysis.
FPGA Design | System Engineering Project Lead
Tallinn University of Technology
07.2017 - 06.2019
- Outlined work plans, assessed timelines for projects and promoted use of best practices.
- Developed architectural designs for FPGA systems, leading to high-performance and energy-efficient solutions
- Implemented and verified custom IP blocks and subsystems, contributing to development of innovative design solutions.
- Outlined work plans, assessed resources, and determined timelines for projects.
- Managed engineering projects with consistent record of on-time and under-budget delivery.
- Identified and implemented most acceptable resolutions to complex engineering problems.
- Developed design test-benches for simulation tests and digital signal processing verifications.
- Optimized and integrated bus/communication standard protocols.
- Evaluated innovative technologies to keep our system design ahead of competition
- Completed comprehensive code compliance evaluations for system design projects.
- Coordinated project team members to deliver high-quality projects within specified timeframes.
- Communicated regularly with executive team members to deliver pertinent details related to progress status and direction for projects.
Education
Doctor of Philosophy in Earth and Space Science and Engineering -
York University
Toronto, Canada06.2024
Master of Science in Computer and Systems Engineering -
Tallinn University of Technology
Tallinn, Estonia06.2019
Master of Science in Instrumentation Technology -
St. Petersburg Electro-Technical University
St. Petersburg, Russia06.2018
Bachelor of Engineering in Electronics and Communication Engineering - Electronics And Communication Engineering
All Nations University
Eastern Region, Ghana05.2014
Skills
- Hardware and Software system design
- System debugging and deployment
- Experience with satellite system architecture
- SoC/FPGA design verification, UVM, and system integration
- Proficient in C, MATLAB, Git, Python, VHDL, Verilog, TCL
- Xilinx Vivado, Vitis SDK, ModelSim, QuestaSim, ISE, Vitis HLS
- HDL design and verification
- Digital Signal Processing
- Project coordination and documentation
- Leadership skills
- Team management
- Detail-oriented
- Excellent communication skills
- Performance and scalability optimizations
Accomplishments
- Ranked in the Top 10% of C++ experts by Testdome.
- Research Excellence Award, SPIE USA, 2018.
Languages
English
Native or Bilingual
Industry-based Projects
- FPGA-based GPS receiver design for earth observation integrating an RF front-end with FMC, SPI, and UART interfaces (ongoing design optimizations)
- FPGA-based DSP module for ultrasound detection (completed) from Iota Biosciences
- FPGA-based AI-driven Traffic Control System (personal project - ongoing AI model updates)
- FPGA-based 5G signal processing module - adaptive beam-forming (completed)
- SW development of GPS receiver in C++ and MATLAB (completed)
- Advanced denoising and FFT module for FPGA design (completed)
- FPGA-based temperature control system (completed) from Starship Technologies
- Customized processor system designed using FPGA logic (completed)
- FPGA-based clock synchronizers (completed) from Starship Technologies
Certification
- LinkedIn Assessment for C++, LinkedIn – 2022
- Modern Python 3 Bootcamp, Udemy - 2023
- Designing a Processor with Verilog HDL and Xilinx Vivado, Udemy - 2022
- System Design Using Verilog, Udemy – 2021
- VHDL Programming and Function Verification, Udemy – 2021
Timeline
Hardware/Software Design Team Lead
York University
12.2019 - Current
SoC/FPGA Project Lead
York University
08.2019 - Current
FPGA Design | System Engineering Project Lead
Tallinn University of Technology
07.2017 - 06.2019
Doctor of Philosophy in Earth and Space Science and Engineering -
York University
Master of Science in Computer and Systems Engineering -
Tallinn University of Technology
Master of Science in Instrumentation Technology -
St. Petersburg Electro-Technical University
Bachelor of Engineering in Electronics and Communication Engineering - Electronics And Communication Engineering
All Nations University
- LinkedIn Assessment for C++, LinkedIn – 2022
- Modern Python 3 Bootcamp, Udemy - 2023
- Designing a Processor with Verilog HDL and Xilinx Vivado, Udemy - 2022
- System Design Using Verilog, Udemy – 2021
- VHDL Programming and Function Verification, Udemy – 2021
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