Yao Luo

• Led AWS EC2 infrastructure and supply security monitoring team, enhancing system resilience through proactive measures.
• Owned distributed validation service to verify AWS server compositions against BOM, preventing unauthorized components.
• Developed hybrid service architecture integrating hosted services with AWS microservices for improved functionality.
• Operated scaled distributed systems supporting AWS data center regions and ODM manufacturing sites.
• Drove cross-team alignment among hardware engineering, data monitoring, and security teams, streamlining processes for improved collaboration.
• Collaborated with ODM and infrasec teams to effectively mitigate supply chain risks, ensuring security and compliance.
• Directed architectural design roadmap planning while mentoring engineers to foster professional growth.

• Led development of validation infrastructure for CPU, memory, and PCIe systems for all AWS server assets.
• Managed PCIe interconnect reliability for critical data paths on accelerator platforms, ensuring optimal performance.
• Reduced PCIe-related AFR via firmware automation and validation improvements
• Translated hardware requirements into automated validation frameworks and test suites that can be applied to different AWS server types.
• Developed telemetry-driven monitoring dashboards and metrics from BMC/BIOS telemetry data to enhance system visibility.
• Facilitated collaboration across hardware, firmware, and software teams to ensure hardware reliability.

• Over six years of industry experience as Verification IP Developer.
• Technical lead/co-architect of three different Cadence Verification IP products (PCIe/CXL/DisplayPort).

- Co-Architect of Cadence PCI-Express Gen6 Verification IP product family.

• Architecturing design of the Transaction Layer packing/unpacking for Gen6 Flit Mode TLP.
• Integration and Data Encryption (IDE) support of Cadence PCIe Gen5/6/CXL 2.0 VIP.
• DOE/CMA/SPDM/ADISP support for IDE Authentication and data protection.
• HKDF-Expand/AES-GCM algorithm modeling for SPDM Secure Session handling.
• Participated in the re-architecture of pkt processing/routing between PCIe Transaction Layer and Data Link Layer.

- Co-Architect of Cadence Compressed Express Link (CXL) Verification IP product family.

• Developed and implemented IDE support for CXL.Cache/Mem Flit protection, enhancing security for CXL 2.0.
• Implemented Data Link Layer Retry mechanism for CXL 1.1.
• Implemented Alternate Protocol negotiation on Cadence PCIe Gen 5 VIP for CXL 1.1.
• Implemented Virtual LSM mechanism for CXL 1.1.

- Technical lead of Cadence DisplayPort Verification IP product family.

• Researched/designed/implemented architecture/function blocks/interface of Verification IP for PHY Repeater.
• Implemented HDCP 1.3/2.2 Authentication/Encryption over DisplayPort in SST/MST mode.
• Implemented multiple Link Layer/PHY Layer sub-systems for Dp/eDp.
• Implemented Link Training/Power Management/Link Quality Pattern testing for Dp/eDp.Technical lead and co-architect of PCIe, CXL, and DisplayPort platforms
• Co-architected infrastructure for PCIe Gen5/6 and CXL, facilitating integration and performance improvements across product lines.
• Developed IDE security modules (AES-GCM, SPDM, CMA)
• Led DisplayPort platform development (PHY, link, HDCP)
• Built system-level models for high-speed interconnects
• Grew from IC to technical lead, mentoring engineers and influencing architecture