Summary
Overview
Work History
Education
Skills
Timeline
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Xinyi Zhou

Hamilton,Ontario

Summary

Personal Background: Currently the forth year Computer Engineering Co-op Student in McMaster University.

Relevant Coursework:Computer Architecture, Digital Communication Systems, Embedded Systems, Digital System Design, Operating Systems, Numerical Methods for Scientific Computing

Progress: A cumulative grade point average of 11.1 on a 12.0 scale (around 3.9 on a 4.0 scale). Deans' Honour List (2022/2023/2024)

Overview

2
2
years of professional experience

Work History

ASIC Digital Design Intern

Synopsys Canada
Markham, Ontario
02.2024 - Current
  • Developed and productized an end-to-end Synopsys PrimeTime-PX power sign-off methodology for PCIe 7.0 PMA (TX/RX) targeting 2 nm / 5 nm nodes: integrated SAIF-based activity from both RTL and gate-level simulation, Liberty PVT libraries (TT/SS/FF), and SPEF parasitics; packaged the flow in Tcl/Python so it can be reused consistently from block to top level.
  • Established measurement procedures that separate dynamic and leakage power and eliminated common methodology errors (clock-gating observability, glitch power, uninitialized nets, library mismatches). On a critical project, after timing closure with DI/STA, reduced the post-synthesis vs. post-route power discrepancy from 55% to 44%, aligning reports across stages.
  • Characterized corner scaling across TT/SS/FF and operating conditions; produced per-corner ratio tables for post-synthesis and post-route netlists and delivered dashboards to support placement/CTS/ECO trade-offs, which stabilized multi-corner power reports and improved reproducibility for the physical team.
  • Delivered production tooling (×3): (1) SAIF preparation/validation scripts adopted by the back-end team; (2) a DV cluster-queue relief utility that improved workflow throughput by ~20% and increased nightly capacity; (3) a Perl→Verilog code generator for TX/RX front-end design that removed repetitive boilerplate, improving engineer efficiency by ~15% and raising the regression pass rate from ~55% to >95%.

Hardware Image Decompressor

McMaster University
Hamilton, Ontario
09.2023 - 12.2024
  • Designed and implemented an FPGA-based image decompression pipeline on the DE2-115: UART stream → external SRAM buffer → Verilog finite-state-machine decoder → VGA output at 320×240; functionality validated in ModelSim and on hardware.
  • Realized the codec reverse path—lossless decode → de-quantization → inverse DCT → upsampling → RGB—and applied RGB→YUV 4:2:0 chroma subsampling; reduced framebuffer/data footprint by ≈33% vs 24-bit RGB while meeting visual fidelity requirements.
  • Met tight area/performance constraints with four shared 32-bit multipliers and dual-port RAM; time-multiplexed scheduling raised hardware-multiplier occupancy to 77.84% in Phase-1 and 97.32% in Phase-2 (occupancy = percentage of active compute cycles).

Software-Defined Radio

McMaster University
Hamilton, Ontario
01.2024 - 04.2024
  • Implemented a real-time FM stereo + RDS receiver on Raspberry Pi 4 (C++) using a command-line pipeline (rtl_sdr | app | aplay); converted RF 2.4 MS/s IQ → IF 240 kS/s → audio 44.1/48 kHz via a fractional resampler; multi-threaded RF/audio/RDS paths keep 22 ms audio buffers within processing time.
  • Designed the stereo baseband: 19 kHz pilot PLL with all-pass delay alignment to reconstruct 44.1 kHz, 2-channel audio; delivered reproducible configs and stabilized playback by fixing a real-time underrun (build-flag issue).
  • Implemented the RDS chain—subcarrier extraction, clock data recovery, root-raised-cosine detection—at 2,375 symbols/s, decoding PI/PTY program fields end-to-end

Education

Bachelor of Engineering - Computer Engineering

McMaster University
Hamilton, ON
06.2026

Skills

  • HDL & EDA: Verilog / SystemVerilog; Synopsys PT / PTPX, Design Compiler, VCS, Verdi; SAIF, SPEF, SDC; ModelSim; Intel Quartus
  • Programming & Modeling: Python, C/C, Tcl, Perl, Bash; MATLAB / Simulink; Git, CMake; Linux; JAVA
  • Embedded & Hardware: ARM Cortex-M4（MSP-432E401Y, FRDM-K64F）, Raspberry Pi 4; UART / I²C / SPI; OrCAD; PSpice / LTspice; Digilent Analog Discovery 2（WaveForms）
  • Languages: Mandarin (native), English (fluent), Cantonese

Timeline

ASIC Digital Design Intern

Synopsys Canada
02.2024 - Current

Software-Defined Radio

McMaster University
01.2024 - 04.2024

Hardware Image Decompressor

McMaster University
09.2023 - 12.2024

Bachelor of Engineering - Computer Engineering

McMaster University

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