3-Bit Binary Sign-Extended Adder/Subtracter:
Utilized Xilinx Vivado Suite for Verilog code development, simulation, and FPGA implementation in a lab focused on designing a 3-bit binary sign-extended adder/subtracter. Created and modified code, generated Xilinx Design Constraints (XDC) files for pin assignments, and performed synthesis for optimal FPGA mapping.
T-Bird Tail light control:
Utilized Xilinx Vivado Suite for Verilog code development, simulation, and FPGA implementation in a lab focused on designing a traffic light control system (tBird). Edited Verilog modules to create a half-clock signal and synchronize light changes. Ran behavioral simulations to validate circuit functionality and generate waveform diagrams. Conducted synthesis, implemented on FPGA, and programmed the device to observe the light system using on-board switches.
Simulating an RLC response using Multisim Live:
Utilized Multisim for RLC circuit frequency domain response and time domain response. Created circuits, adjusted components, and simulated responses. Analyzed frequency response using AC sweep, graphing magnitude and phase. Transitioned to time domain response, examining underdamped, overdamped, and critically damped cases.
Google Books Dataset Project (Python):
Collaborated within a team of 4 for course project, focusing on iterative design, implementation, and testing of a Python program analyzing a subset of the Google Books dataset. Key responsibilities included:
CPRT (Carleton Planetary Robotics Team) Project:
Software:
Hardware:
Circuit Design & Analysis:
Programming:
Relevant Courses: