Todd Tope
Castro Valley
Summary
Developer adept at creating new programs and solutions for SOC physical design clients. Knowledgeable in the full range of RTL-to-GDS flow development, with both Synopsys and Cadence expertise. Successful technology career history comprising more than 15 years.
Overview
20
20
years of professional experience
Work History
Senior Principal Application Engineer
Cadence Design Systems
02.2021 - Current
- Worked with Intel account as flow developer for Cheetah 2 design system. Developed system to run entire Intel flow at CDNS with comparatively small testcase package.
- Crafted and delivered hierarchical synthesis and layout flow adaptation to Cheetah 2, running on full SOC designs and committing partitions and feedthroughs, and timing budgets
- Assumed lead of IFS (Intel Foundary Services) Reference Flow for multiple technologies, and was responsible for full reference flow developement and regressions.
Physical Design Flow Lead
Intel Corp
03.2016 - Current
- Lead flow developer for 4 SoC projects in two different technologies, in-house and external
- Responsibilities include porting over-arching physical design flow system (a version of Synopsy's
- Lynx flow management system)
- Lynx covers the entire rtl to gds flow
- Also added:
- Primetime Distributed Multi-Scenario Analysis(DMSA) Timing and DRC ECO flow
- Conformal Functional ECO flowCPU Cross Server Calibre DRC flow
- Base Layer DRC checking preroute to determine viability of floorplan
- Spare flop and smart-gate-array DCAP insertion flow to support any metal-only fix (Freeze Layer) ECOs we might encounter
- Highly parameterized and tested power mesh creation script and flow which creates correct-by- construction, DRC clean, IVD clean power structures at the block level
- Push-button, Zero-DRC flow from beginning to end on regression testcases
Design Automation Engineer
Intel Corp
11.2014 - 02.2016
- Responsible for all aspects of 16-fin-fet/28nm, power and layout methodology
- Produced power mesh used at all levels of Large basestation chips and the 16nm testchip
- Responsible for specification of voltage budgets across the power delivery network (PDN) and reliability verification (RV) with Redhawk
- In addition, I was the designer of several blocks required on these chips, including the pvtmon (process monitor), cpm (critical path monitor), refclock (digital section), tempsens (digital section), and superIO (digital section)
- Design role for pvtmon/cpm was from RTL, simulation, implementation and test program production
- Other contributions include crafting and maintaining the filler insertion flow, crafting and maintaining the Intel mini-fiducial flow, and primary LVS/DRC cleaning of the Frodo testchip
- Primary duties with UPF flow support continued at Intel, and several designs utilizing my UPFs and UPF support were taped out.
Principal Design Engineer
LSI Corp
03.2009 - 10.2014
- Responsible for all aspects of 16-fin-fet, 28nm, and 40nm power architecture for LSI SoC customer designs
- Lead and trained engineering staff around the country in the discipline of low-power UPF design
- Crafted complete 16FF approach to dual-rail memory mesh architectures and automatic
Principal Design Engineer
LSI Logic
01.2008 - 01.2009
- Responsible for development and implementation of full physical design UPF Power closure methodology from RTL to GDS2 for SoC design flow at LSI using largely Synopsys tools
- Duties included training and publicizing UPF flow to bring the two engineering units from the merger of LSI and Agere into the same flow
- Direct consultation on designs for physical closure, including timing, congestion, and LVS/DRC closure.
Manager I Manager
Clock Methodology Group
01.2004 - 01.2008
- Responsible for development and implementation of full physical design closure methodology from RTL to GDS2 for SoC design flow at LSI
- Designed and lead 4 testchips during this time in the 3M gate range using 90nm and 65nm technologies
- One of these testchips contained the full implementation of a multiplier clocked by the MultiGig rotary clock.
Education
Graduate - Honor Graduate
USAF Electronic Warfare Training Academy
Skills
- Coding:
- Tcl/Tk , Python, Perl, C-shell, Verilog, UPF,
- Tools:
- Cadence Innovus, Genus, Conformal LEC, Stylus flow system
- Synopsys Lynx, RTM Manager
- Perforce, IC Manage data management systems
- Synopsys IC-Compiler/2, Design Compiler/DCNXT
- PrimeTime, StarRCXT, Redhawk, Totem, ICV
- VCS, Verdi, Hspice, Formality, VLP, Calibre
Timeline
Senior Principal Application Engineer
Cadence Design Systems
02.2021 - Current
Physical Design Flow Lead
Intel Corp
03.2016 - Current
Design Automation Engineer
Intel Corp
11.2014 - 02.2016
Principal Design Engineer
LSI Corp
03.2009 - 10.2014
Principal Design Engineer
LSI Logic
01.2008 - 01.2009
Manager I Manager
Clock Methodology Group
01.2004 - 01.2008
Graduate - Honor Graduate
USAF Electronic Warfare Training Academy
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