TARUN KAKAR

• Supporting Synopsys Controller IP customers. Working closely with customer design and verification teams, supporting them through PCIe Controller IP support, integration activities of SNPS Controller, including debugging, reviews and product support.
• Providing product training to customers, reviewing customer RTL requirements, helping generate custom RTL.
• Supporting customer for product related questions, customer simulation debug and bridging the gap between customer and RnD.

• SOC DV GPU NAV

1. North Bridge Input/output (NBIO) DV

• Complete ownership of NBIO Verification including Test Plan
• GEN4 Bring Up for PCIE
• Coordination with NBIO Subsystem Team for any integration updates, fixes and feature updates at SOC for NBIO
• Execution of SOC Callouts from NBIO Subsystem and driving them to closure
• Bring up testcases, Regression Debug, closure of functional and toggle coverage, scoreboard updates.

2. POWER DV

• Bring up of power features specific to NBIO in form of API/Function call.
• Created testcases for Low Power Feature TestPlan
• Complex end to end SOC Scenarios with multiple power features.

3. PCIE IP Verification for Gaming Console

• Lead PCIE IP Verification
• Execution of PCIE IP Test Plan
• Driving coverage to 100% closure, report generation and exclusion file
• Defining assertions and implementing them using bind.
• Improved legacy cover points and assertions thereby reducing simulation time.
• Lead a team of 3 resources and delivered PCIE IP Verification on milestones agreed.

4. Entropy Validation for AES (Advanced Encryption Standard)

• Verify the entropy values for AES input and output.
• Black Box Verification of AES Entropy
• Responsibility included testbench creation and random constraint input generation.
• Processing of output data and delivering results to customer

• Project: Top level Verification of SRCv Based Chips
• Environment: VHDL for RTL, Specman for Test Cases and Verification
• Responsible for:
• Top level verification of SRCv based chips. This included SRCv x24 and x16 port chips checking reset protocol, connectivity, and inbound/outbound data flows.
• Developed test cases for new feature verification/protocol from top level prospectus.
• Releasing top level IP releases and managing regressions.
• Reporting bugs, enhancements and tool related issues to the concerned designer or tool vendor.
• Tool Used: Ncsim for Simulation (Specman for Verification), Simvision for waves, vmanager for regression.

• PCIe Wrapper Verification and IOMMU IP Verification
• Environment: Verilog for RTL, C for Test Cases and System Verilog for the Functional Coverage and Assertions
• Definition of Functional Coverage points for Interface Protocol for PCIE and IOC blocks and implementation coverage points defined for PCIE.
• Assertion Definition and Implementation for blocks involved in PCIE wrapper verification.
• Verification of Impedance Arbiter and Compensation Block (Test Cases and Assertions)
• Test planning, test case creation and debugging for various Clock and Power Management Block of PCIE/Memory Management Unit features.
• Functional Coverage and Assertion Definition, Implementation and Review for IOMMU Block
• Generation, Review of Code Coverage with Designers/other team members
• Implementation of generator and checker for automatic verification of various features of PCIE
• Regression management, maintenance and debugging of test cases.
• Tool Used: VCS for simulation and Coverage Reports, Novas Verdi for debugging and waveform, Bugzilla for bug reporting, perforce for version control.

• Network Traffic Generator (Verification IP)
• Environment: System Verilog for the creation of the test environment
• Study of the Ethernet 802.3 Protocol and the Internet and Transport Layer Protocols
• Identification of the features to be added in the test environment.
• Creation of Test Unit Plan for the Verification Environment
• Coding of complete verification environment (Monitor, Generator, Driver and Scoreboard)
• Writing assertions for the protocol checking
• Coding of the cover group for coverage analysis
• Testing of the complete Verification Environment
• Coding of Perl Scripts for the Automation of the Verification Environment
• Tool Used: VCS for simulation and dve as debugger.

• Cyber Tool Validation
• Environment: The Cyber Work Bench (Tool) tested in a verification environment in a UNIX Platform.
• Identification of test cases (test plan)
• Writing test cases in SystemC and BDL (Behavioral Description Language)
• Identification of bugs and reporting bugs and issue for options and attributes in the Tool to the development team at NEC RL
• Written Perl Scripts for reallocation of Test Cases from old Environment to New Environment
• Mentored two junior members in the team and managed quality delivery to the client.
• Tools Used: Cyber Tool, iverilog and vcs for simulation, gtkwave for waveform viewing.

• Project: Verification PCI Express Base 1.1:
• Verification of PCI Express (MAC, TL, DL Layer)
• Environment: The Denali model/Denali monitor was used as verification IP to functionally verify the RTL
• Writing test cases for the MAC Layer of PCIe in Verilog
• Identification of bugs and reporting bugs and issue to the Client
• Review of the test cases done by the other members of the team
• Writing Perl Scripts for the Automatic Generation of Test Cases
• Tools Used: ncvlog used for simulation and coverage, simvision used for waveform viewing.