Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
Best NCG project award
Patent Draft Recognition (for the DRAM cache management innovation)
Generic

Susheela Hegde

Kitchener,ON

Summary

Embedded Systems professional with 8+ years of experience in firmware development, hardware/firmware validation, and system-level debugging. Skilled in C, C++, Python, and scripting for real-time embedded systems. Proficient in SoC bring-up, unit/bench testing, and integration/stress testing with a focus on debugging and validating firmware-hardware interactions. Experienced in RTOS, pre- and post-silicon validation, and debugging across FPGA, ARM, and x86 platforms. Strong track record of diagnosing and resolving critical firmware and hardware issues.

Overview

10
10
years of professional experience

Work History

Firmware Verification Engineer Intern

Synopsys
01.2025 - 08.2025

▪ Validated SERDES and PCIe6 firmware on pre-silicon test environments (FPGA and test chips) by running validation test scripts and debugging reported issues related calibration and adaptation.

▪ Ported and enhanced C-based debug and logging features from legacy firmware to new builds, enhancing traceability and improving validation efficiency across subsystems.

▪ Collaborated with IP and firmware teams to analyze firmware–hardware interactions and resolve system-level

validation issues.

Staff Firmware Engineer

Western Digital
03.2018 - 11.2023

▪ Developed and debugged firmware for hardware-software co-design on ARM/RISC-V–based HDD controllers, using embedded C for low-level implementation.

▪ Designed and validated low-level firmware modules for power management, queue scheduling, and cache memory subsystems in HDD controllers, ensuring performance and reliability.

▪ Conducted thorough testing, debugging, and validation of firmware using Python and Bash scripting, VS Code C unit test frameworks, FPGA emulation, and post-silicon platforms, ensuring product quality and performance.

▪ Developed and maintained comprehensive documentation, including design specifications, test plans, release notes, and low-level firmware diagrams.

▪ Participated in code reviews, provided constructive feedback, and mentored junior engineers on best practices in embedded development.

▪ Contributed to the full product development life cycle, from concept through FPGA validation, firmware implementation, and post-silicon production support.

Senior Software Engineer

Sony
08.2015 - 08.2017

▪ Ported open-source Linux kernel patches into Snapdragon’s Yocto-based build environment and developed

firmware extensions in C to ensure reliable module initialization, hardware/firmware stability, and system integrity.

▪ Conducted pre-silicon validation and debugging of system stability on Snapdragon platforms, identifying

and resolving firmware device driver issues.

▪ Developed a boot level debugging tool in ARM assembly to diagnose early boot problems and trace memory

corruption issues efficiently.

Education

Post-Graduate Certificate - Embedded Systems Develoment

Conestoga College Institute of Technology And Advanced Learning
Kitchener
08-2025

Bachelor of Engineering - Computer And Information Sciences

B.V.B College of Engineering
Hubli, India
06-2015

Skills

  • C and C
  • Proficient in Git and SVN
  • Version control and automation
  • Experienced in Python programming
  • Product lifecycle oversight
  • System integration expertise
  • ARM and x86 architecture knowledge
  • Cortex-M assembly programming
  • Cache memory management
  • Continuous integration
  • Coverage analysis

Accomplishments

  • Introduced enhanced DRAM cache management techniques that improved storage system read/write performance by 15%, earning selection for the Western Digital Tech Showcase.
  • Led a team of 10+ engineers in developing, testing, and validating firmware features for DRAM cache management, including low-level design, task breakdown, and unit/bench validation.
  • Documented hardware specifications into Plant-UML-based low-level designs, enabling the team to implement ~70% of features successfully.
  • Debugged and fixed memory corruption bugs using bench and unit test validation, achieving high reliability with 80% of changes causing no side effects, minimizing regression risk.
  • Resolved critical firmware and memory issues at the fastest rate among a cross-functional team, validated via unit and bench testing, and received team awards for outstanding contributions
  • Developed award-winning early kernel debugger in ARM Assembly/C, presented at Sony Global India Tech Exhibition and in Japan, accelerating early boot debugging and memory corruption analysis.

Timeline

Firmware Verification Engineer Intern

Synopsys
01.2025 - 08.2025

Staff Firmware Engineer

Western Digital
03.2018 - 11.2023

Senior Software Engineer

Sony
08.2015 - 08.2017

Post-Graduate Certificate - Embedded Systems Develoment

Conestoga College Institute of Technology And Advanced Learning

Bachelor of Engineering - Computer And Information Sciences

B.V.B College of Engineering

Best NCG project award

Project: Early Kernel Debugger Tool (NCG Program, Sony)

  • Objective: Diagnose early kernel boot issues on ARM-based SoCs, even before UART initialization, when kernel output is minimal.
  • Technical Contributions:
    Developed firmware in ARM assembly and Embedded C for early-stage kernel debugging.
    Leveraged early_printk, ftrace, and function prologue/epilogue hooks to trace and identify faulty code paths.
    Added a feature to log the memory address of the function causing the issue during boot, providing actionable insights where normally only “starting kernel” was visible.
  • Impact & Recognition:
    Enabled rapid detection and debugging of early boot failures and memory corruption issues.
    Awarded first prize among all New College Graduate projects.
    Selected to present at Sony Global India Tech Exhibition and in Japan.
  • Skills/Tech: ARM Assembly, Embedded C, Linux Kernel, Early Boot Debugging, ftrace, early_printk

Patent Draft Recognition (for the DRAM cache management innovation)

Project: DRAM Cache Management Optimization (Western Digital)

  • Objective: Improve HDD read/write throughput through enhanced DRAM cache management techniques.
  • Technical Contributions:
    Designed and implemented firmware-level DRAM cache optimization algorithms in Embedded C.
    Conducted unit and bench testing and python scripts to validate reliability and performance under diverse workloads.
  • Impact & Recognition:
    Achieved 15% improvement in storage system read/write performance.
    Selected for Western Digital Tech Showcase.
    Drafted for patent submission for novel cache management techniques (first draft, recognized even if not granted).

Skills/Tech: Embedded C, DRAM cache, HDD firmware, python, SOC-bring-up, FPGA/post-silicon validation

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Susheela Hegde