Sandesh Shetty

Client: AMD, Markham

• Collaborated with the PCIE verification team to identify, debug, and resolve RTL bugs.
• Conducted regular regression testing on the latest PCIe 6 RTL using the legacy test environment, enabling early identification of design flaws in the latest iteration. This proactive strategy facilitated prompt resolution of design issues throughout the development cycle.
• Initiated Jira for bugs found, leading to detection of duplicate bugs found in new and old environment, resulting lesser debug cycle.
• Enhanced my verification expertise through hands-on experience in the PCI Express (PCIe) environment.

Client: Alphawave, Ottawa

• Contributed to enhancing the OTN design by implementing new features tailored to meet the client's requirements.
• Proposed modifications to the design to accommodate the integration of the new feature and appreciated by the client.

• Served as the Lead Designer within the DSP core team, overseeing the development of L2 and ETM IP designs.
• Engaged in collaborative architectural discussions with teams based in San Diego and Austin to enhance project development and alignment across locations.
• Conducted comprehensive reviews of IP architecture and design, incorporating new features across multiple SOCs to ensure seamless integration and optimal performance delivering under tight timelines.
• Oversaw RTL design of L2 and ETM for numerous cores destined for integration into Qualcomm's roadmap, ensuring adherence to rigorous Lint, CDC and Coverage checks.
• Took charge of implementing inline assertions within the design, significantly expediting issue resolution through enhanced debugging capabilities and facilitating faster turnaround times.

• Senior Designer with Multimedia team leading Memory interface and Local Cache design in India working closely with Global teams
• Coordinated technical requirements, scheduling and solution development with GPU/IP architects in Canada and USA
• Brainstormed with client IP owners to understand requirements and implement optimal solution for Local Cache
• Drafted documentation for understanding encoding and decoding of Pixels through memory interface
• This would help future designers to make changes at ease
• Awarded spotlight award.

• Conducted engineering studies on design for products, associated and subsystems components and structures
• IEEE 802.11 Protocol understanding.

• RTL designer for USB and DMA IP team.
• Architecture ,design and integration of DMA block.
• Worked with FPGA bring team to bring up IP on XILINX platform
• FPGA IP debugging with chipscope and Vivado.
• Designer for AXI and AHB bus interconnects.