Sai Kiran
Vancouver,BC
Summary
Seeking to contribute and serve as a key DFT expert for an organization where I'll be able to challenge myself, best utilize my potential, experience and education to enhance my knowledge and thereby contribute effectively and efficiently to achieve organizational goals.
A result oriented professional with overall 7+ years' experience in Design for Testability (DFT). Insightful knowledge of RTL pre-scan ability checks and scan implementation. Insightful knowledge of MBIST insertion, validation in RTL level as well as Gate level with and without SDF. Insightful knowledge of ATPG pattern generation, coverage analysis.
Overview
7
7
years of professional experience
Work History
DFT Engineer consultant
Intel Canada - Contractor
03.2024 - Current
- Tools used : TestKompress,VCS,Verdi/DVE,Xcelium.
- Worked on Coverage improvement using Tessent.
- Pattern generation using SDC.
- Resolved SDF simulations issues using VCS/Xcelium.
- Retargeting pattern generations and simulations for top level.
- Generated SOC Level extest patterns.
- Worked on SOC Level Gate Level Simulations with SDF.
- Developed a simulation automation script using Perl.
DFT Engineer consultant
HuMetis Technologies - Contractor
03.2023 - 02.2024
- Tools used : modus,xcelium,simvision,tessent mbist
- Coverage improvement of scannable flops using spyglass.
- Involved in ATPG for block level and top level (ICtest) using Modus.
- Gate level simulations using multicore as well as single core xcelium.
- Implemented Gate level simulations by enabling MISE in xcelium.
- Worked on MBIST implementation and verification.
- Worked on LBIST implementation and simulation flow using Modus.
DFT Engineer consultant
Qualcomm India - Graphene Pvt. Ltd.
02.2021 - 12.2022
- Tools used : Design accelerator,spyglass,yield accelerator,vcs,verdi,simvision,DVE,conformal
- RTL based MBIST implementation through Synopsys SMS (Star Memory System) flow in subsystem level.
- Memory grouping analysis based on defined rules and PD feedback.
- Logic Equivalence Check (LEC) between pre and post MBIST inserted RTL.
- Ownership of RTL based MBIST validation using SMS generated testbench for default and custom algorithms.
- Ownership of Gate level unit delay and timing simulations to validate MBIST.
- Memory repair analysis through soft repair in SoC level.
- Developed a perl script for clock,memory,pll checkers.
- Involved in FTRV(First Time Run Vectors) runs.
- Pattern generation for SoC level simulations.
- Worked on pattern conversion setup for ATE format.
- Memory repair analysis (BIRA) subsystem level through fault injection.
- Worked closely with the ATE team for complete support and debug.
- Worked on Post Silicon Validation.
DFT Consultant
Inhouse Project India - UST GLOBAL Pvt. Ltd.
04.2018 - 01.2021
- Tools used: modus,xcelium,simvision,DC compiler
- involved in ATPG pattern generation
- Analyzing and Fixing DRC issues
- Worked on ATPG Coverage improvement
- Owned the spyglass DFT rule checks and worked closely with the RTL design team on fixing the Pre DFT design bugs and to improve scan ability
- Owned block level scan insertion and fixing pre and post DFT DRC violation
- Developed perl script for check list
DFT Trainee
Tessolve Semiconductor Private
08.2017 - 03.2018
- Completed DFT training with labs, basics of STA ,perl scripting and verilog.
Education
Bachelor of Technology -
JNTU
Hyderabad, India01.2017
Skills
- RTL level DFT rule checks, to achieve high scan insertion rate, and spyglass coverage
- Worked closely with the RTL team to fix any DFT design bugs, through spyglass DFT rule checks
- Subsystem level scan implementation pre and post DRC analysis
- ATPG and simulations
- MBIST implementation using Synopsis SMS flow
- MBIST validation using SMS generated testbench for unit delay and timing simulations
- Memory repair analysis (BIRA)
- Tester debug support and conversion of patterns to tester format
- LBIST implementation and simulations at subsystem level
- Good knowledge in perl scripting, TCL shell scripting and shell scripting
Languages
English
Professional Working
Timeline
DFT Engineer consultant
Intel Canada - Contractor
03.2024 - Current
DFT Engineer consultant
HuMetis Technologies - Contractor
03.2023 - 02.2024
DFT Engineer consultant
Qualcomm India - Graphene Pvt. Ltd.
02.2021 - 12.2022
DFT Consultant
Inhouse Project India - UST GLOBAL Pvt. Ltd.
04.2018 - 01.2021
DFT Trainee
Tessolve Semiconductor Private
08.2017 - 03.2018
Bachelor of Technology -
JNTU
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