Roy Business Phone Pavloff

One Man Shop

Metal Work

Body Work

Painting

Machine Work

Welding

Sales

Finance

Analog layout Design

1998 to 2002 IBM Auburn Ca

IBM analog products group

Sr Mask Design Engineer

direct employee

2003 to 2006 IBM Austin Tx

Contract Mask Design Engineer

funded by IBM, SONY.Hatachi

8 Core Microprocessor

Cell Broadband Engine

I was responsible for all Analog

layout contractors work

I planed all of analog functional block level

with some of the critical cell level circuity

on the chip

tools Mentor graphics,Cadence

Attached performance review.

Responsibilities

Hardware and software evaluations

Project lead

Hiring Contractors

project Layout progress

schematics status

cell plan status

cell draw status

cell DRC status

cell LVS status

cell sign off status

category status as a percentage

on the project or chip

I developed a methodology for

scheduling layout time based on

certain criteria at the cell level

block level and chip level

all data driven

results are percentage driven

I also trained mask designers

I was also doing the real work

of mask design layout

hardware

sun Microsystems work stations

tools Cadence

Contracting Positions

analog and Digital

processors,memories

1990-1992

Digital Equipment Corp

two different projects

1992-1994

Intel Corp

Folsom,Oregon

several different Projects

1994=1997

Advanced Micro Devices

Michael Van Buskirk

Flash Memories

Project Migration

1997-1998

Hal Computer

1 project

Layout supervisor

responsibilities

9 layout people

layout productivity

cell level

block level

chip level

Cadence tools

Micropower systems 1974-1976

layout designer

technology's Bipolar C-MOS Molygate

low and high voltage

tools Mylar layout and rubbly cutting

plan and layout

2 chips analog bipolar

6 chips C-MOS Molygate

LSI was anything over 1000 transistors

Synertech 1976-1978

Sr Layout designer

technology C-MOS silicon gate

Low Voltage

1 chip plan and layout

Calma GDS 2

Memorex 1978-1980

Large storage division

Sr Layout Designer

reverse engineering of IBM

systems of a chip

Bipolar Technology Analog

Computer Vision tools

High powered scope with filters

for schematic generation

plan and layout of chip

1980-1981

Fairchild Semiconductor

PROM products

Process bipolar ECL technology

Calma GDS 2

Draculs DRC

my chip ran clean

promoted to supervision

1981-1983

Teledyne Semiconductor

Supervisor of CAD and Layout

Plate ordering ,defect quality of plates

Brought our design group up on

layout methodologies of

computer aided layouts

GDS 1 and developed menu driven

layout with some physical design

generation of layout structures

to cell library design rules

1983-1984

Maxim Integrated Products

was one of the original 11 hired

when the company started

Sr Layout Designer position

we taped out 21 products our first year

Del Mar High School 1966 t0 1970

2 years of Mechanical Drafting

1 year of Technical Illustration

1 year Architecture

California Academy of Drafting 1971-1972

Electro Mechanical Drafting

1000 hour course A

Mos Design Drafting B+