Summary
Overview
Work History
Education
Skills
Languages
Publications
Timeline
Hi, I’m

RAJALAKSHMI T R

Coquitlam,Canada

Summary

Possess about ten years of experience in the field of teaching and five years of Industrial experience. Completed Doctorate in the research work of CNTFET memories. Strong organizational skills. Thorough understanding of the subject with the ability to convey the same to the students. Good communication and comprehension abilities. Served as Reviewer in several journals.Have published Technical papers in several journals.Having good knowledge in creating detailed technical documentation that enhances user understanding and operational efficiency. Utilizes clear and concise language to communicate complex information effectively. Strong understanding of technical writing principles and best practices.

Overview

19
years of professional experience

Work History

Intel

SOC DESIGN ENGINEER (DFT)
2022.08 - 2024.04 (1 education.year_Label & 8 education.months_Label)

Job overview

  • Company Overview: Xeon Networking Group at Intel
  • DFT implementation across scan insertion, pattern generation, and gate-level simulations
  • Perform ATPG stuck-at and transition fault pattern generation & coverage analysis
  • Handle block-level Pattern generation and simulate those patterns
  • Work on timing and no-timing simulations of ATPG patterns
  • Experience in debugging timing simulation failure
  • Xeon Networking Group at Intel

Insemi Technologies,Skandysys, Altran Technologies

DFT ENGINEER
2018.01 - 2022.08 (4 education.years_Label & 7 education.months_Label)

Job overview

  • DFX Verification works
  • Develops Pre-Silicon DFX validation tests to verify system that will meet design requirements
  • Validating the DFX environment and design by running regressions for suites like JTAG, CLOCK, ATPG, SCAN, COUNTER
  • Pattern Simulation & debugging simulation mismatches
  • Responsible to run regression and make sure the design and test bench are stable
  • Validating and debugging Gate level simulations to identify the RTL Vs Netlist design bugs
  • Debugging the issues using the Verdi tool
  • DFT implementation across scan insertion, pattern generation, and gate-level simulations
  • Perform ATPG stuck-at and transition fault pattern generation & coverage analysis.
  • Handle block-level Pattern generation and simulate those patterns.
  • Work on timing and no-timing simulations of ATPG patterns.
  • Experience in debugging timing simulation failure.

Altran Technologies

ANALOG DESIGN ENGINEER
2018.01 - 2019.05 (1 education.year_Label & 4 education.months_Label)

Job overview

  • Have developed and released Standard Cell libraries
  • Worked on multiple lower technology nodes
  • Worked on Various Cad View generations as required by Standard cell libraries
  • Ability to work in a wide variety of industry-standard modelling formats including Liberty (CCS), Verilog, Milky way, Spice
  • Red hawk view generation for libraries, library characterization and compilation of the standard cell
  • Hands-on experience in Standard cell characterization

P.E.S University,Dayananda Sagar University

ASSISTANT PROFESSOR
2015.07 - 2018.12 (3 education.years_Label & 5 education.months_Label)

Job overview

  • Handled undergraduate and Post Graduate classes
  • Supervised and assisted the students in project works
  • Published research results, and monitored students' performance
  • Contributed to the efficient management and administration of the department and the college

P.S.V College of Engineering and Technology

ASSISTANT PROFESSOR
2012.08 - 2015.07 (2 education.years_Label & 11 education.months_Label)

Job overview

  • Handled undergraduate course classes
  • Supervised and assisted the students in project works
  • Published internal, term, semester and research results, and monitored students' performance and provided appropriate suggestions and training for betterments

Adhiyamaan College of Engineering

ASSISTANT PROFESSOR
2007.06 - 2011.10 (4 education.years_Label & 4 education.months_Label)

Job overview

  • Provided instructional assistance and monitored student progress
  • Committed as ISO internal auditor and as exam co-ordinator
  • Served on academic and administrative committees as assigned
  • Contributed to the efficient management and administration of the department and the college
  • Have attended several training programmes and workshops which enriched the knowledge in research

Vellore Institute of Technology

LECTURER
2005.07 - 2006.10 (1 education.year_Label & 3 education.months_Label)

Job overview

  • Handled postgraduate courses in VLSI Design
  • Guided Postgraduate projects
  • Attended several Faculty training programmes

Education

Anna University
India

Ph.D. from VLSI Design
2017-05

SASTRA University
India

Master of Technology from VLSI Design
2005-05

Skills

  • Content Editing
  • Collaborative writing
  • Technical editing
  • Instruction writing
  • Document formatting
  • Technical research
  • User guides
  • Problem-solving abilities

Languages

English
Native or Bilingual
Tamil
Native or Bilingual
Hindi
Professional Working

Publications

  • Rajalakshmi, T.R. and Sudhakar, R., 2017. Impact of Single Event Upset on Voltage and Current Behaviours of CNTFET SRAM and a Comparison with CMOS SRAM. Journal of Circuits, Systems and Computers, 26(02), p.1750020.
  • Rajalakshmi, T.R. and Sudhakar, R., 2016. A novel carbon nanotube FET-based bulk built-in current sensor for single event upset detection. Sādhanā, 41(5), pp.489-495.
  • “Single Event Upset Detection and Hardening Schemes for CNTFET SRAM –A Review” Journal of Engineering Science and Technology Review 8 (5) (2015) 49-56.
  • Rajalakshmi. T.R. and R. Sudhakar, “Fault and reliability analysis of CNTFET SRAM in the presence of Single Event Upset” American Journal of Applied Sciences 11 (8): 1343-1350, 2014.

Timeline

SOC DESIGN ENGINEER (DFT)

Intel
2022.08 - 2024.04 (1 education.year_Label & 8 education.months_Label)

DFT ENGINEER

Insemi Technologies,Skandysys, Altran Technologies
2018.01 - 2022.08 (4 education.years_Label & 7 education.months_Label)

ANALOG DESIGN ENGINEER

Altran Technologies
2018.01 - 2019.05 (1 education.year_Label & 4 education.months_Label)

ASSISTANT PROFESSOR

P.E.S University,Dayananda Sagar University
2015.07 - 2018.12 (3 education.years_Label & 5 education.months_Label)

ASSISTANT PROFESSOR

P.S.V College of Engineering and Technology
2012.08 - 2015.07 (2 education.years_Label & 11 education.months_Label)

ASSISTANT PROFESSOR

Adhiyamaan College of Engineering
2007.06 - 2011.10 (4 education.years_Label & 4 education.months_Label)

LECTURER

Vellore Institute of Technology
2005.07 - 2006.10 (1 education.year_Label & 3 education.months_Label)

Anna University

Ph.D. from VLSI Design

SASTRA University

Master of Technology from VLSI Design

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