Oliver (Siyuan) Cao
Markham,Canada
Summary
Hardware engineer with 4+ years of experience in PHY IP validation, firmware automation, and RTL DFT design. Skilled in bridging silicon bring-up and pre-silicon verification for high-speed LPDDR4/5 memory interfaces. Strong hands-on background in lab validation, firmware scripting, and RTL-level design/debug, with proven collaboration across design, validation, and customer support teams.
Overview
5
5
years of professional experience
Work History
Senior IP Validation Engineer
The Six Semiconductor Inc.
05.2022 - 12.2025
- Designed and implemented DFT features in LPDDR4/5 PHY RTL to enhance testability and silicon debug efficiency.
- Collaborated with design and verification teams to validate PHY functionality across multiple process corners.
- Developed Python automation tools for regression and pattern generation, improving validation throughput.
- Supported pre-silicon verification and silicon correlation, ensuring alignment between RTL simulation and lab behavior.
- Contributed to next-generation PHY feature definitions and internal verification infrastructure.
IP Validation Engineer
The Six Semiconductor Inc.
05.2021 - 04.2022
- Conducted lab validation and performance evaluation of LPDDR4/5 PHY IPs.
- Developed and maintained Python-based test frameworks for bring-up, calibration, and regression automation.
- Diagnosed and resolved signal-integrity and timing issues using oscilloscopes, logic analyzers, and JTAG.
- Provided customer bring-up support and documentation for PHY integration and debug.
Memory Team (PEY Internship)
AMD
01.2018 - 01.2019
- Supported validation and automation development for memory subsystem projects.
- Assisted in customer bring-up and issue reproduction.
- Built software tools to streamline validation workflows.
Education
Bachelor of Applied Science (B.A.Sc.) - Electrical and Computer Engineering
University of Toronto
01.2020
Skills
- Effective communication
- Equipment qualification
- Testing protocols
Languages
English
Native or Bilingual
Timeline
Senior IP Validation Engineer
The Six Semiconductor Inc.
05.2022 - 12.2025
IP Validation Engineer
The Six Semiconductor Inc.
05.2021 - 04.2022
Memory Team (PEY Internship)
AMD
01.2018 - 01.2019
Bachelor of Applied Science (B.A.Sc.) - Electrical and Computer Engineering
University of Toronto