Summary
Overview
Work History
Education
Skills
Patents
References
Timeline
Generic

Mark Hammes

Vallejo

Summary

Accomplished Principal Program Manager with a proven track record at Microsoft and Marvell Semiconductor Inc, adept in Program Management with background in SOC Design. Excelled in leading cross-functional teams, reducing program risks, and delivering key projects like Hololens and Surface on time and budget. Expert in collaboration and driving innovations in hardware security IP, enhancing product competitiveness.

Overview

36
36
years of professional experience

Work History

Principal Program Manager

Microsoft
Mountain View
01.2016 - Current
  • As a Program Manager Leader I have successfully managed multiple SOC Silicon programs from concept (Business Justification Planning) through to Production release
  • This includes working with team members distributed geographically and partnering with 3rd party vendors
  • Bringing Best Practices learned into organization to help mitigate program risks
  • Specifically the requirement for detailed reviews at key junctures
  • Aspects of the programs encompassed: Working with SOC Customer(s) to provide development details (technical and financial) for their planning/submissions
  • Pulling together all program facets in initial planning for evaluation and approvals
  • Working with 3rd party vendors including contract negotiations, feasibility studies/evaluations (both technical and business)
  • Working with Legal to develop SOWs and Financial aspects
  • Through the execution phases covering initiation of design through to production release working with multi-disciplined teams in Marketing, Engineering, Operations and 3rd party vendors
  • Formulation of schedules with trackable milestones and risk analysis with mitigation plans
  • Reporting of programs to senior management and working to understand priorities of programs
  • Successes specifically have been in providing various SOCs to main product requirements (Function, Budget, Schedule) including Hololens and Surface products
  • I have also most recently been Program managing the development of Microsoft HW Security IP which is utilized in many SOC programs across Microsoft and other 3rd party customers
  • This has opened up many opportunities to collaborate with many external (to Microsoft) teams in delivering IP into their programs while maintaining Microsoft security requirements
  • A key part of this responsibility has been working with the customers on Agreements and SOWs working with legal

Sr. Program Manager

Marvell Semiconductor Inc
Santa Clara
04.2011 - 01.2016
  • Company Overview: [Marvell purchased Solarflare division which resulted in change in employer]
  • Program Management of multiple programs of ICs encompassing both HW and SW deliverables
  • Scope of programs covers initiation of design through to production release working with multi-disciplined teams in Marketing, Engineering, Operations
  • Formulation of schedules with trackable milestones and risk analysis with mitigation plans
  • Reporting of programs to senior management and working to understand priorities of programs
  • Bringing Best Practices learned into organization to help mitigate program risks
  • Specifically the requirement for detailed reviews at key junctures
  • [Marvell purchased Solarflare division which resulted in change in employer]

Sr. Program Manager

Solarflare Communications
Irvine
05.2008 - 04.2011
  • Included within the Program Plans were the following elements: schedule, budget, cost analysis, deliverables (internal and external), ownership and accountability assessments, risk analysis with mitigation plans
  • Detailed goals with measurable metrics provided for a tracking mechanism and status reporting
  • For the key programs communications with executive management to the customer was also an added responsibility
  • Formulation of best practices for Program scheduling, tracking, and risk analysis/mitigation
  • Also, working with 3rd party contract firm located in India as part of development team to deliver products which included spending considerable time in India managing team on site in an extended role as technical project lead

Program Manager

Conexant Systems
San Diego
04.2006 - 04.2008
  • Program Management leadership role in building a team of Program Managers responsible for IC development projects and working to established methodologies and tools to establish measurable objects and goals
  • Methodologies were rolled out to worldwide teams in India, China and US with training
  • This role also entailed the complete reporting of all programs through to executive management and working with the Program Managers and technical teams in communicating expectations
  • This specifically required the creation of a full Program Plan encompassing all activities ranging from IC development, Software, Firmware, Hardware, Product & Test, and Customer interactions/deliverables

Design Engineering Manager

JSI Microelectronics
McClellan
02.2003 - 04.2006
  • This role within the small organization entailed responsibility for ALL design activities including working with Marketing to communicate the abilities of the company to acquire new business
  • Specific Design responsibilities include quoting all design work for new projects
  • Working with the foundries and tool vendors to provide the tools and libraries needed
  • Actual hands on design work including RTL, Simulation, Synthesis, STA and Backend Layout and verification flows

Technical Project Lead

Intel / Level One Communications
Sacramento
06.1998 - 02.2003
  • Responsible for defining and evaluating design options to meet business objectives together with managing design activities towards delivering functional VLSI design of an Ethernet Physical Layer device
  • Reduced cost of manufacture of design by 50% from previous generation
  • Evaluated multiple options of design architecture and manufacturing processes to conclude optimum choice

Program Manager

Intel / Level One Communications
Sacramento
06.2000 - 04.2002
  • Responsible for managing full program activities across multiple functional groups towards the delivery of final product with Design, Test, Manufacturing and Marketing plans
  • Led effort to bring new Program Management Practices into group
  • Developed full program schedule of all functional activities with their interdependencies and tracking, which facilitated early warning indicators of issues
  • Created Risk Score Card with mitigation plans for High Risk items – one risk item came true and the availability of a mitigation plan reduced recovery time

Methodology Manager/Timing Lead

Intel / Level One Communications
Sacramento
10.1999 - 06.2000
  • Responsible for pulling together unified design (digital) methods and practices across all development projects
  • Success on previous projects in Synthesis and STA methods were documented and migrated to new projects
  • Learning curves and repeat mistakes were reduced
  • During this period a critical project was staffed with all available resources with the Lead Timing Analysis position being assigned to myself
  • The methods established were applied to the project and with a target date given I formulated a revised methodology to obtain closure on timing
  • Revised methodology included going to a 2 Sigma spread on timing models
  • Yield effects were understood and accepted in the business plan, as TTM was critical here

Design Manager/Technical Project Lead

Intel / Level One Communications
Sacramento
06.1998 - 10.1999
  • Managed a group of Senior designers (5) whom worked on various projects
  • Setting up of training plans and reviews together with mentoring of the engineers
  • Also, responsible for the Synthesis/STA effort on a project
  • A make flow was created which resulted in reducing the time from design change to netlist production to under 1 day
  • Moved into Chip Lead of the Multiport Repeater project when previous lead left company
  • I held this role during final design phase and verification through tapeout and Silicon Verification
  • Technically I was responsible for writing ECOs towards the initial tapeout to fix the timing and any other functional bugs, which regressions brought up

Design Engineering Manager

Analog Devices
Wilmington
04.1996 - 05.1998
  • Responsible for various design activities including Team Leadership towards the design of Motor Control ICs
  • Rebuilt design group through recruiting activities
  • Reduced design time on next generation devices through better design practices

Staff Design Engineer

Brooktree Corporation
Austin
09.1994 - 04.1996
  • Responsible for various design activities concerning the design of PC Multimedia Chip Set
  • I performed team leader activities on a project which was joint with a foreign 3rd party and so included an understanding of their flows (Full Custom) and the need for merging our Verilog/Synopsys within their environment and visa-versa

Snr VLSI Design Engineer/Team Leader

Texas Instruments Limited
Bedford
11.1988 - 09.1994
  • Responsible for various design activities concerning the design cycle of Full Custom Graphics Processors/DSPs
  • Design flow encompassed the writing of Rtl and Behavior models followed by Schematic entry and Layout generation using std cell and datapath compilers together with some script generated Hand Drawn layout
  • I have co-authored papers and submitted patents regarding various aspects of the 320C80

Education

PhD - A Node Interface For Parallel Processing

Nottingham Polytechnic
Nottingham, England

BSc - Electronic, Computer and Systems Engineering

Loughborough University of Technology
Loughborough, England

Skills

  • Microsoft Project
  • Powerpoint
  • Excel
  • Word
  • Sharepoint
  • SOC Design
  • Circuit Design
  • Verilog
  • Timing Analysis
  • GDS Generation
  • Program Management
  • Collaboration With Engineering Teams

Patents

  • Pipelined data processing including program counter recycling, 5,922,070
  • Pipelined data processing including interrupts, 5,724,566
  • Pipelined data processing including instruction trace, 5,564,028

References

References available upon request.

Timeline

Principal Program Manager

Microsoft
01.2016 - Current

Sr. Program Manager

Marvell Semiconductor Inc
04.2011 - 01.2016

Sr. Program Manager

Solarflare Communications
05.2008 - 04.2011

Program Manager

Conexant Systems
04.2006 - 04.2008

Design Engineering Manager

JSI Microelectronics
02.2003 - 04.2006

Program Manager

Intel / Level One Communications
06.2000 - 04.2002

Methodology Manager/Timing Lead

Intel / Level One Communications
10.1999 - 06.2000

Technical Project Lead

Intel / Level One Communications
06.1998 - 02.2003

Design Manager/Technical Project Lead

Intel / Level One Communications
06.1998 - 10.1999

Design Engineering Manager

Analog Devices
04.1996 - 05.1998

Staff Design Engineer

Brooktree Corporation
09.1994 - 04.1996

Snr VLSI Design Engineer/Team Leader

Texas Instruments Limited
11.1988 - 09.1994

PhD - A Node Interface For Parallel Processing

Nottingham Polytechnic

BSc - Electronic, Computer and Systems Engineering

Loughborough University of Technology

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