Maria Anjali Kennedy Chettiar
Folsom,CA
Summary
RTL Design Engineer with 5+ years of experience architecting and implementing ASIC RTL for high-performance Intel CPUs. Expertise in CPU microarchitecture, Reorder Buffer (ROB) design, SystemVerilog RTL development, and performance optimization for out-of-order processors. Skilled in end-to-end RTL development, including microarchitecture definition, RTL implementation, CDC/RDC verification, synthesis, static timing analysis (STA), low-power design, and functional verification. Proven success delivering production silicon across multiple Intel processor generations while improving performance, power, and area (PPA).
Overview
7
7
years of professional experience
Work History
CPU RTL Design Engineer
Intel
Folsom
08.2021 - Current
- Led microarchitecture definition and ASIC RTL implementation for a performance monitoring feature in Intel Panther Lake processors, enabling improved utilization analysis of CPU core resources.
- Designed and implemented ASIC RTL in the CPU Reorder Buffer (ROB) using SystemVerilog to support Processor Event-Based Sampling (PEBS) for virtualized environments, improving performance profiling capabilities for enterprise customers.
- Architected and implemented RTL enhancements within the CPU Reorder Buffer (ROB) to support relamination events, improving execution efficiency for complex instruction flows.
- Optimized ROB microarchitecture by reducing Load Lock instruction retirement latency by six cycles, improving processor throughput and execution performance.
- Optimized CPU RTL for Performance, Power, and Area (PPA) through clock gating, power gating, logic optimization, and clock merging techniques while maintaining functional correctness. Performed SpyGlass Lint and CDC/RDC verification to eliminate structural RTL issues and ensure synthesizable, production-ready ASIC designs.
- Conducted linting and CDC/RDC checks using tools like SpyGlass to ensure clean RTL before synthesis.
- Debugged RTL issues identified during simulation, synthesis, and design reviews, resolving functional and timing issues before tape-out.
- Developed SystemVerilog Assertions (SVA) and contributed to UVM-based verification environments to validate RTL functionality and improve verification coverage.
- Performed functional simulation using Synopsys VCS and Verdi while utilizing PrimeTime for power analysis and static timing analysis (STA).
CPU Core Integrator
Intel
Folsom, CA
01.2020 - 06.2021
- Delivered multiple client and server SoC integration milestones by coordinating RTL integration, CDC cleanup, interface validation, and backend model synchronization.
- Supported pre-silicon and post-silicon debug activities, resolving critical integration and functional issues to enable successful tape-outs.
- Contributed to successful tape-in of Intel's 14th Generation processor by supporting CPU core integration, validation, and design readiness activities.
CPU Core RTL Design Intern
Intel
Folsom, CA
07.2019 - 12.2019
- Supported RTL development and debugging for the CPU Instruction Fetch and Decode (FIT) pipeline using SystemVerilog.
- Applied knowledge of CPU architecture instruction and decode pipelines to support RTL development and debugging activities.
- Led latch-to-flop conversion across Front-End RTL to improve timing robustness, reliability, and synthesis quality.
- Used Synopsys Verdi for waveform analysis and RTL debugging to identify and resolve functional design issues.
Education
Master of Science - Electrical Engineering
University of Southern California
Los Angeles, USA12-2019
Bachelor of Technology - Electronics and Telecommunication Engineering
University of Mumbai
Mumbai, India06-2017
Skills
- Programming Languages:
SystemVerilog, Verilog, Python, Git - RTL Design:
CPU Microarchitecture, ASIC RTL Design, Reorder Buffer (ROB), Pipeline Design,
Performance Monitoring (PEBS/PMON), Out-of-Order Execution - Verification:
SystemVerilog Assertions (SVA), Functional Verification,
CDC, RDC, SpyGlass Lint
- Design & Timing:
Synthesis, Design Compiler, PrimeTime,
Static Timing Analysis (STA),
Timing Closure,
Low Power Design,
RTL Optimization - Protocols & Architecture:
AXI,FIFO,Cache Coherency (MOESI),DFT - EDA Tools:
Synopsys VCS,Verdi,Design Compiler,
PrimeTime,
Vivado,Cadence Virtuoso
Websites
Timeline
CPU RTL Design Engineer
Intel
08.2021 - Current
CPU Core Integrator
Intel
01.2020 - 06.2021
CPU Core RTL Design Intern
Intel
07.2019 - 12.2019
Master of Science - Electrical Engineering
University of Southern California
Bachelor of Technology - Electronics and Telecommunication Engineering
University of Mumbai