Summary
Overview
Work History
Education
Skills
Accomplishments
Personal Information
Disclaimer
Timeline
Generic
Manogna GUMMADI

Manogna GUMMADI

San Jose

Summary

Design Verification Engineer with extensive experience at AMD, focusing on IP and SoC verification. Proficient in SystemVerilog and UVM, delivering enhanced system reliability and efficiency. Skilled in cross-functional collaboration, providing robust testing solutions that guarantee data integrity and performance.

Overview

11
11
years of professional experience

Work History

Service Provider

AMD
San Jose
02.2025 - Current

Project: ATC verification within NVMe Subsystem.

  • Enhanced system reliability by coding various error scenarios in NVMe subsystem.
  • Created interrupt service routine to facilitate efficient task management within ATC.
  • Refined ATC block drivers, monitors, and scoreboard to ensure robust functionality during testing.

Member of Technical Staff

Mirafra Technologies
BANGLORE
02.2024 - 01.2025

Project: SOC Bringup.

  • Executed integration of 20+ Synopsys VIPs at SoC, followed by thorough end-to-end testing using test cases.
  • Designed UVM testbench architectures for each VIP to enhance testing efficiency.

Member of Technical Staff

AMD
BANGLORE
08.2020 - 02.2024

Project 1: IOMMU in MI300 SoC.

  • Executed comprehensive test plans for MI300 IOMMU, encompassing sanity, error, and smoke tests.
  • Verified nested address translations while implementing cache management and security protocols.
  • Authored functional coverage documentation to ensure thorough feature testing verification.

Project 2: NBIO in MI300 SoC.

  • Supported team during subsystem bring-up for MI300 NBIO project.
  • Coded sequences for different request types.
  • Tested end-to-end data paths and added data integrity scoreboard checks.

Project 3: IOMMU in MI450 SoC.

  • Collaborated on virtualization aspects of MI450 IOMMU project.
  • Developed IOMMU test plan with extended features to enhance testing scope.

Member of Technical Staff

Chelsio Communications
Bangalore
01.2018 - 08.2020

Project: Cache

  • Developed and verified a 2MB cache verification model
  • Exercised cache mechanism features like cache flush, cache update, and eviction.
  • Project 2: T7 Soc

Design Verification Engineer

Prodapt ASIC services (Formerly Innovative Logic)
09.2015 - 12.2017

Project1: DMA(Direct Memory Access)

  • Developed and verified the MEMORY-IO, IO-MEMORY, MEMORY-MEMORY, and IO-IO Write and Read operations with different data sizes

Proejct2: AXI4

  • Verified Basic Read/Write Transactions, Burst Transactions,Error Handling and Data Integrity

Intern Engineer

Maven Silicon VLSI Training Center
Bangalore
06.2014 - 12.2014

Project : AHB

  • Developed single master and slave, SV and UVM testbench to enhance testing capabilities.
  • Created sequences for testing various request types with supported burst lengths and sizes.

Education

Bachelor of Technology - Electronics And Communications Engineering (ECE)

Acharya Nagarjuna University
Guntur, Andhra Pradesh
04-2013

Skills

  • IP and SoC verification
  • SystemVerilog and SVA expertise
  • UVM certification
  • Simulation tools proficiency, like Synopsys, Cadence, and Questa
  • Industry-standard protocols knowledge
  • AXI, AHB, DMA, and IOMMU virtualization
  • PCIe and CXL fundamentals
  • Bug reporting tools Jira, Bugzilla

Accomplishments

  • Received the Individual Excellence award from Chelsio Communications 2019.
  • Received AMD Spot Light Award for 2021
  • Received AMD Executive Spotlight Award for the MI300 project's successful completion in 2022
  • In 4 years, received two promotions in AMD i.e: 1. Contractor to Sr.Silicon Verification Engineer and 2. Sr.Silicon Verification Engineer to MTS.

Personal Information

Disclaimer

I hereby declare that all the details furnished are true to the best of my knowledge.

                                                                                                

                                                                                                                     Thanks,

                                                                                                                     Manogna

Timeline

Service Provider

AMD
02.2025 - Current

Member of Technical Staff

Mirafra Technologies
02.2024 - 01.2025

Member of Technical Staff

AMD
08.2020 - 02.2024

Member of Technical Staff

Chelsio Communications
01.2018 - 08.2020

Design Verification Engineer

Prodapt ASIC services (Formerly Innovative Logic)
09.2015 - 12.2017

Intern Engineer

Maven Silicon VLSI Training Center
06.2014 - 12.2014

Bachelor of Technology - Electronics And Communications Engineering (ECE)

Acharya Nagarjuna University
Manogna GUMMADI