Summary
Overview
Work History
Education
Skills
Certification
Websites
Research Projects
Timeline
Generic

Manini Gunjal

Cupertino

Summary

Dynamic professional with 9+ years of technical expertise at Intel, specializing in hardware design and process optimization. Led innovative tool development and cross-functional initiatives related to clock domain crossing tool. Skilled in managing IP SoC handoff, and enhancing vendor communication to ensure quality and efficiency in complex team environments.

Overview

10
10
years of professional experience
1
1
Certification

Work History

SoC Team

Intel
Santa Clara
03.2024 - Current
  • Led R2G tool development as senior member of SOC team. Designed automations for execution and updated a web-based indicators for over 60 partitions. Led junior engineers in applying best design practices. Ensured a seamless transition to the Silicon Debug team with structured handoff processes.

Audio IP Team

Intel
Santa Clara
09.2019 - 03.2024
  • Served as integration lead, facilitating communication between internal and external sub-IP teams. Negotiated conditions and timelines with delivery teams to ensure project alignment. Addressed common issues to foster knowledge sharing across teams.
  • Led team as key technical mentor, fostering skill development and project success.
    Orchestrated vendor communications to synchronize Audio IP clocking tasks efficiently.
    Pioneered Reset Domain Crossing (RDC) implementation for advanced spyglass checks.
    Executed architectural reset flow changes to accommodate RDC requirements. Analyzed data (violations in six digits) to filter through actual issues. Worked with Synopsys on minimizing this noise in future versions, iteratively suggesting new features. Collaborated with designers to resolve the actual errors within the short timeline.
  • Delivered effective management of two or more ongoing projects, guaranteeing minimal impact on cycle times.
  • Championed extensive reviews, and enabled the team to resolve outstanding issues, resulting in reduced project cycle time.

Ethernet IP

Intel
Santa Clara
03.2018 - 03.2019
  • Managed Tools Flow and Methodology (TFM), executing release process encompassing tool flow and model preparedness to SoC.
  • Analyzed and ensured the quality of deliverables by fixing RTL, CDC, LINT, and SCAN issues.

USB IP

USBA
Folsom
09.2015 - 03.2018
  • Owned clock domain crossing flow for the USB team, working on all Questa CDC violations pertaining to IP.
  • Conducted in-depth evaluations alongside microarchitects for every project while acquiring knowledge of design flow
  • Implemented scan check for USB IP, which was part of an initiative to improve scan coverage for SoC. The project asked for continuous debugging and complete knowledge of scan tool flow, which included Spyglass DFT, DC, and ATPG. It involved enabling a new tool for scanning.
  • Carried out scalability of IP as part of integration tasks, and provided SoCs with all the CDC support needed.

Education

Bachelor of Engineering - Electronics and Telecommunication

Vishwakarma Institute of Technology
Pune, India

Master of Science - Electrical Engineering

Stony Brook University
Stony Brook, NY

Skills

  • Cycle time reduction
  • Problem solving
  • Process improvement
  • Hardware design
  • Tools flows and methodologies
  • Vendor communication
  • Stakeholder management
  • Clock domain crossing
  • Collaboration skills
  • Technical mentoring
  • Attention to detail

Certification

Product Management Studio Certification - UC Berkeley (Apr 2022)

Research Projects

Product Management Canvas (2022): Building product management canvas for Netflix customer focusing on customer value propositions, market segmentation, customer journey mapping etc. Wrote PR/FAQ for the same.

Research Assistant at Stony Brook University (2014): Worked under Prof. Peter Milder. 2D Convolution on FPGA- Part of a project on classification of ImageNet using Convolutional Neural Networks.

Timeline

SoC Team

Intel
03.2024 - Current

Audio IP Team

Intel
09.2019 - 03.2024

Ethernet IP

Intel
03.2018 - 03.2019

USB IP

USBA
09.2015 - 03.2018

Bachelor of Engineering - Electronics and Telecommunication

Vishwakarma Institute of Technology

Master of Science - Electrical Engineering

Stony Brook University

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Manini Gunjal