MAITHRI REDDY EDDULA

Project and Technology Enabler

• Directed multicultural project support for global design team, addressing EDA issues effectively.
• Enhanced CAD environment configuration to boost operational efficiency in integrated circuit design.
• Actively contributed to script development, improving design quality and accelerating R&D processes.
• Co-developed AI agent for JIRA ticket classification, increasing productivity by identifying operational gaps.
• Created utility programs and conducted gap analysis to resolve designer issues swiftly.
• Collaborated with stakeholders to alleviate tool-PDK bottlenecks, ensuring timely project delivery.

Project and Technology Enabler

• Supported a diverse global design team with debugging EDA issues, interfacing with external suppliers, and configuring the CAD environment.
• Designing, developing, troubleshooting, or debugging software tools and flows for the development of integrated circuits.
• Developed utility programs to automate repetitive CAD tasks and personally debugged complex DRC, LVS, EMIR, simulation, and extraction runs.
• Coordinated technology setup for new critical process nodes and high-priority customers, ensuring seamless environment initialization.
• Co-owned the DB Integrity Flow which guarantees all IP products are produced with proven, traceable data, prevent accidental and unauthorized changes, enable thorough audits, and ensure compliance with customer or internal quality audits.
• Architected and built a training platform from scratch that allows teams to plug in training modules, configure from available training modules, create training plans, and assign them to the users. Assignment, reminders, overdue notifications, and completion notifications are automatically sent, and completion tracking is also achieved by quizzes and acknowledgments.
• Guided junior peers through complex technical aspects of the CAD domain, establishing standardized procedures and best practices.

• Contributed to multiple iPDK development projects spanning 4 nm to 180 nm technology using Python and Tcl.
• Developed essential PDK features, including Abutment, Stretch Handles, MPPs, and EPCs.
• Executed HSPICE and Spectre simulations for thorough performance analysis.
• Implemented schematic migration flow for TSMC CDRF certification requirements.
• Updated and validated custom compiler tech files across various nodes and foundries.
• Enabled integration of Quick Start Kit for reference 10 nm PDK.
• Created validation scripts for sdlSimInfo, parameter display, editability, and callbacks in PDK.
• Trained and mentored new team members to improve technical skills.

• Contributed to multiple iPDK development projects ranging from 4nm to 130nm.
• Delivered PDK on schedule, facilitating further engagements with Samsung.
• Enabled PDK features including Abutment, Stretch Handles, and MPPs.
• Executed simulations for Hspice models to validate performance.
• Developed Editable Pcells to meet specific requirements for Samsung.