Khyati Malhotra
Summary
Highly skilled, dedicated and driven with a strong passion for excellence, Physical Design Engineer with 7 years of experience in leading-edge semiconductor companies. Strong background in all aspects of physical design, from netlist handoff to GDS tape-out, with a track record of optimizing power, performance, and area (PPA) metrics. Adept at project management, team leadership, process improvement and collaborating with cross-functional teams to deliver innovative solutions that exceed expectations.
Overview
8
8
years of professional experience
Work History
Senior Lead Physical Design Engineer
Qualcomm
11.2019 - Current
- Worked on a total of 12 (full ownership) and supported 4 additional projects across 3-11nm nodes.
- Full PnR ownership with some PV fixing responsibilities in multiple projects.
- Mentored team members to achieve technical excellence and project success.
- Managed a team of 8 PD engineers, overseeing 15 blocks twice (2 projects alongside implementation)
- Led PD (floorplan + PnR for 4 (tiles + SoC Top) projects, ensuring on-time successful tape-out.
- Developed automation scripts and optimized design methodologies for enhanced productivity.
- Established effective communication channels between cross-functional engineering teams, promoting collaboration on shared objectives and goals.
- Implemented multi-voltage designs and tackled netlist to GDS challenges.
- Handled large-scale blocks with 7 M instance count with expertise in aggressive timing/PV/PDN closure during eco cycles.
- Successfully addressed complex PD challenges, including Congestion management, High TDRC quantum reduction, Clock balancing, H Tree implementation, custom CTS methodology, Transport Inv/Buf Implementation, CrossTalk, Noise.
Application Engineer
Cadence Design Systems
07.2018 - 10.2019
- Collaborated with R&D teams to enhance timing QoR for advanced automotive designs.
- Developed flow enhancements and optimized H-Tree strategies to improve design efficiency.
Intern
STMicroelectronics
06.2017 - 12.2017
- Assisted in internal tool development and provided EDA tool support.
- Evaluated and tested new features as requested by the designers.
Education
B.Tech in Electronics And Communication
YMCA University of Science And Technology
Faridabad, Haryana, India06-2018
Senior Secondary Examination (CBSE)
D.A.V Public School
Faridabad, Haryana, India03-2014
Secondary Examination (CBSE)
D.A.V Public School
Faridabad, Haryana, India03-2012
Skills
- Floorplanning
- Placement
- Clock Tree Synthesis
- Routing
- PV Fixing
- SoC PnR
- Block Level PnR
- Functional/Timing ECO
- Cadence Innovus
Accomplishments
- Prestigious "RISING STAR" award from Qualcomm VP, India for outstanding contributions.
- 3 technical papers selected for QC conferences.
- Multiple appreciation tokens received in 5.3 years of work in Qualcomm.
- SHINE recognition for testing and validating designs on upcoming Cadence tool releases.
- Hosted TECH Day at STMicroelectronics.
Additional Information
- Problem-solving
- Debugging
- Attention to detail
- Leadership
- Time management
- Adaptability
Timeline
Senior Lead Physical Design Engineer
Qualcomm
11.2019 - Current
Application Engineer
Cadence Design Systems
07.2018 - 10.2019
Intern
STMicroelectronics
06.2017 - 12.2017
B.Tech in Electronics And Communication
YMCA University of Science And Technology
Senior Secondary Examination (CBSE)
D.A.V Public School
Secondary Examination (CBSE)
D.A.V Public School