Joseph Anthony Alvarez

• Moved to Motor Driver Group (2 ICs, both general purpose grade, but different in supply)
• Made Substitute Group Leader; in charge of overall skill improvement
• Introduced AMS and Verilog-A in chip-level simulation that emulates 3-phase BLDC motor
• Became resource person on Verification Freshman Training, Batches 5 and 6
• Became member of 5S Working Group; In-charge of maintaining floor's PCB Assembly Area

Overall:

• Produced, planned, and managed circuit designs, including modification of existing IPs or designing from start
• Planned and managed transistor-level and gate-level / pre-fabrication verification standards such as Corners Simulation, Mixed-mode Simulation (both with Cadence ADE Suite), and Digital Simulation using NCSim, SimVision, and SimCompare for Verilog, Verifault, and IDDq, and verified its accuracy from target specifications
• Planned, modified, and verified layout designs; performed post design rule checks using SX-Meister and PowerVolt
• Planned, managed, and executed various post-fabrication and line establishment test standards such as C-class evaluation, 3-piece evaluation, EDS and FT Test Development and results yield analysis for mass production, and other ISO9001/IATF16949 and AECQ-100 Automotive testing standards (ex. HAST, TCY, HTOL)
• Planned, managed, and verified ESD / TLP Designs; performed failure analyses on various defective devices with ESD/TLP Evaluation, Air Discharge Evaluation, Emission Microscope, and FIB Machine
• Involved in the full IC development of EEPROMs, LCD Segment Drivers, and 3-Phase BLDC Motor Drivers

• Moved to LCD Segment Driver Group (2 Series ICs, one General Purpose, one Automotive)
• Managed, planned, and executed circuit and layout modifications, with emphasis on increase / decrease of COM/SEG, as well as ESD Protection (contributed in designing GCNMOS IP)
• Managed, planned, and executed, Failure Analyses on various ESD failure mechanisms using Photoemission Microscope, FIB Machine, Air Discharge Gun, ESD and TLP Machines
• Contributed to completion of its AECQ-100 Automotive compliance with Quality Assurance Tests

• Trained in LSI Development and then deployed to EEPROM Group (2 IC Series in SPI and uWire Bus)
• Managed, planned, and executed circuit and layout modifications, both in transistor level and gate level
• Executed Digital simulation and produced results using Verilog for Functional verification
• Produced and executed Test patterns for structural tests including Verifault and IDDq; confirmed and mitigated timing violations using SDF Back annotation after P&R
• Contributed to the Test Development (and hands-on debug) and Test Pattern generation
• Earned the Bronze Award for Improvement 2013 for making a C-shell Script for Yield Analysis

• Trained and then deployed to Simulations Group
• Managed and ran Corners Simulation requests in DC, AC, and Transient Analyses
• Executed Transmission Line Pulse Simulations; produced reports necessary for ESD design confirmation
• Made a study of a Switching Regulator Verilog-A-based model its efficiency in dual core computers
• Also done Reverse Engineering of competitor devices and Design Sample Evaluation requests using calibrated laboratory equipment
• Earned the Model Employee Award in 2010