John Kim
San Diego
Summary
Results-driven individual with a solid track record in delivering quality work. Known for excellent communication and teamwork abilities, with a commitment to achieving company goals and delivering exceptional service. Passionate about continuous learning and professional development.
Overview
30
30
years of professional experience
1
1
Certification
Work History
Principal, Yield and Diagnostics Engineer
Qualcomm Technologies, Inc.
San Diego
03.2021 - Current
- Primary analyst for advanced node SoC products yield learning. Lead daily yield debug and diagnostic activity for yield ramp, identifying defect and parametric yield loss mechanisms and driving FA through foundry PFA labs. Incorporate wafersort bin and test details, diagnostics (ATPG and MBIST), and scribe parametric data to evaluate device process windows and centering.
- Forecasted future yield for products to enable corporate supply chain and operations teams to expect future supply, using various data sources, including fab FCC reports, device trends and DBKM early outlook samples incorporating yield modeling techniques.
- Created production data pipelines for extracting data from production STDF test data stream, with augmentation and custom meta data storage including custom Bin grouping for efficient interpretation from product engineering/yield teams.
- Designed and implemented a new automated classification data pipeline to identify EUV mask adder impacted wafers real time, from wafersort data, including cross validation with memory repair details and ATPG/MBIST diagnostics.
- Created and implemented new algorithm for robust spatial signature classification of wafer patterns to cluster wafers into like fail modes.
- Trained users on Yield Explorer applications.
Scientist, Silicon Lifecycle Management Analytics Strategy, Digital Design Group
Synopsys, Inc.
Mountain View
05.2020 - 02.2021
- Strategist for SLM product line specializing in design to silicon integration within the Silicon Lifecycle Management product line.
- Developed new analytic methods to enable a new design aware yield learning practice on production data.
Principal, Applications Engineer, Silicon Engineering Group, Yield Explorer
Synopsys, Inc.
Mountain View
07.2011 - 04.2020
- Developed concept for the two primary strategic projects to implement new features, including feature specification, prototyping, testing and validation.
- Developed several new automated data mining algorithms to identify and classify excursion events for production devices for efficient yield learning.
- Enabled the Yield Explorer (YMS software) R&D group to develop new features and applications to enable faster yield ramps at customer installations using non traditional yield data sources.
- Drove major changes in ATPG scan volume diagnostic methods and analysis applications to improve customer interface and data interpretation. Implemented multivariate analysis solutions to solve complex convoluted fail problems.
- Trained R&D staff on yield methods, and consulted to internal AE teams to solve problems at customer locations.
Senior Manager, Program Management, Solutions Group
Synopsys, Inc.
Mountain View
09.2010 - 06.2011
Director, Program Management
Virage Logic Corporation
Fremont
03.2009 - 09.2010
- (acquired by Synopsys)
Account Director Z-RAM
Innovative Silicon, Inc.
Santa Clara
09.2007 - 02.2009
Engagement Director - Yield Ramp Client Services
PDF Solutions, Inc.
San Jose
09.2003 - 08.2007
Process Integration Engineer, ASTC FEOL Foundry Logic Technologies
IBM Corporation
East Fishkill
04.1996 - 08.2003
Education
M.S. - Electrical Engineering (Microelectronics focus)
Yale University, School of Engineering and Applied Sciences
New Haven, CTB.S. - Chemical Engineering (Electronic Materials option)
University of California at Berkeley, College of Chemistry
Berkeley, CASkills
- Project/Program management
- Technical resource management
- Semiconductor Yield Management
- Yield methods and Yield Modeling
- Practical applications of statistical methods in yield engineering and data analysis
- FEOL process integration/development (STI, Gate, Device, Contact Module)
- ASIC, DRAM and CIS product engineering
- Fab control/manufacturing methods
- Semiconductor industry data analysis tools (Exensio, Spotfire, Yield Explorer, JMP)
- Tcl
- SQL
- Python
- Julia
- PostGreSQL
- SQLite
- Oracle database development for production data management
Publications
- W. Zhou, T. P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson, T. Furukawa. HfO2 and HfAlO for CMOS: Thermal Stability and Current Transport, International Electron Devices Meeting 2001
- Y. Pan, R Desineni, J. Lambert, E. Teoh, T. Berndt, V. Lim, G.S. Huat, J. Kim, S Kekare. SpotMe: Effective Co-Optimization of Design and Defect Inspection for Fast Yield Ramp, Advanced Semiconductor Manufacturing Conference 2013
- J. Kim. Automated Volume Diagnostics for Accelerated Yield Learning in 40nm and below technologies. Korea Test Conference 2013
- V. Simhadri, N. Agrawal, B. Talatam, H. Kim, T. Schink, R. Kuse, M.W. Chai, J. Kim, A. Lazaryan, P. Lin. An Approach for Optimizing Yield of Embedded Memories on Mobile SoC Chips. Electron Devices Technology and Manufacturing Conference (EDTM) 2019.
- K. Lucas, V. Moroz, J. Kim, SH Choi, T. Tsuei, Multi-varied implementations with common underpinnings in Design Technology Co-Optimization. Society of Photo-Optical Instrumentation Engineers (SPIE) 2020
Patents
- G. Goth, J. Kim, V. Nastasi. Self-Aligned Corner Vt enhancement with isolation channel stop by ion implantation. US 20020179997 A1
- R. Jammy, J. Kim, S. Lucarini, G. Mack, C. Parks, D. Riggs. Process for removing dopant ions from a substrate. US 20030066542 A1
- W. Ellis, J. Kim. Technique for forming a contact to a buried diffusion layer in a semiconductor memory device. W0 2010102106 A3
- J. Kim. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation. US 7947543 B2
- J. Kim, B. Gordon, K. Movsisyan, C. Suzor. Extracting attribute fail rates from convoluted systems. US 20140324374 A1
- R. Marutyan, B. Gordon, C. Suzor, J. Kim. Identifying Layout Pattern Candidates. US 9,292,650
- L. Bomholt, X. Lin, J. Kim. Circuit Design Generation, Inspection Apparatus Calibration and Process Control and Yield Management. US Pending, Germany DE102015108244A1
Key Highlights And Skills
- Experienced semiconductor industry strategist in areas of test data integration, foundry/fabless use models and practices, EDA to Silicon integration for the purpose of analytics.
- Successfully yield-ramped several semiconductor process nodes as well as consulted on yield ramps on logic, memory, and CMOS Image Sensor technologies from 0.4um down to 2nm technologies.
- Trained engineers in the areas of yield learning methodology, yield modeling, analysis techniques and ATPG scan volume diagnostics.
- Created new data applications applying various analytical methods and statistical techniques including yield models using both traditional production wafersort data, as well as advanced diagnostic data types such as ATPG and MBIST diagnostics. Currently used in production at the major foundries for root cause identification of fab excursions.
- Implemented data pipelines into a production data warehouse by transforming and augmenting incoming semiconductor data (stdf and other various formats) into usable formats using a variety of languages (Tcl, SQL, Python, and Julia)
Certification
- Senior member IEEE
Timeline
Principal, Yield and Diagnostics Engineer
Qualcomm Technologies, Inc.
03.2021 - Current
Scientist, Silicon Lifecycle Management Analytics Strategy, Digital Design Group
Synopsys, Inc.
05.2020 - 02.2021
Principal, Applications Engineer, Silicon Engineering Group, Yield Explorer
Synopsys, Inc.
07.2011 - 04.2020
Senior Manager, Program Management, Solutions Group
Synopsys, Inc.
09.2010 - 06.2011
Director, Program Management
Virage Logic Corporation
03.2009 - 09.2010
Account Director Z-RAM
Innovative Silicon, Inc.
09.2007 - 02.2009
Engagement Director - Yield Ramp Client Services
PDF Solutions, Inc.
09.2003 - 08.2007
Process Integration Engineer, ASTC FEOL Foundry Logic Technologies
IBM Corporation
04.1996 - 08.2003
M.S. - Electrical Engineering (Microelectronics focus)
Yale University, School of Engineering and Applied Sciences
B.S. - Chemical Engineering (Electronic Materials option)
University of California at Berkeley, College of Chemistry