Jithu Bijoy George

Allreduce IP Verification

• Led verification of Tesla’s first-generation custom Allreduce engine from IP through multi-chip emulation, achieving 100% functional coverage with waivers.
• Architected a multi-platform Python stimulus generator and golden reference model capable of producing valid multi-chip stimulus and checkers for both simulation and emulation.
• Developed a scalable UVM testbench from scratch with reusable checkers, scoreboards, and coverage models.
• Owned test planning, regression triage, and closure of all coverage metrics
• Partnered with RTL and performance modeling teams to detect and resolve key performance bottlenecks ahead of schedule.

DMA Subsystem Verification

• Co-developed the DMA subsystem testbench ensuring correct inter-block synchronization across all test modes.
• Built end-to-end checkers enabling early detection of functional bugs, significantly reducing debug cycles.
• Architected a scalable multi-DMA verification environment spanning multiple SoCs, exposing critical cross-SOC corner-case issues.

RandGen – Standalone SOC Stimulus Generator

• Designed a Python-based random stimulus framework leveraging architectural specifications to produce stimulus and memory vectors, routing data, and checker collateral for DMA verification.
• Created reusable libraries for memory management, preload utilities, system routing, and instruction randomization — greatly reducing test development time.

Slice IP Verification

• Led verification of a custom memory fabric interconnect linking multiple internal NOCs to the memory controller.
• Built a UVM environment with drivers, monitors, checkers, and constrained-random stimulus to achieve full functional and code coverage.

Emulation

• Developed self-checking multi-SOC test flows for Cadence Palladium, reducing manual debug effort.
• Created synthesizable modules to trigger hard-to-reach corner-case scenarios.

• Developed checkers, assertions and scoreboards to verify AXI4 interfaces and NOC connectivity.
• Developed scripts to generate custom stimulus to target corner cases and to perform instruction coverage analysis.

• Designed and integrated a synthesizable AXI4 monitor to be used on the Cadence Palladium Emulator.

• Developed scripts to generate customized logs based on user preference to aid in test debug.