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Seeking challenging career opportunities in VLSI design & Verification domain with an organization of repute.
A competent professional with 11 years of experience in Hardware Design & Verification industry with expertise in Formal and Functional Verification technology. Currently responsible for IP level verification by defining the verification scope, developing the verification infrastructure, test suites and verifying the correctness of the design. Knowledge of all phases of ASIC design methodology. Made strong contributions to successful tape outs of multiple SOCs - using simulation based verification methodologies, formal verification and dynamic Assertion based verification. Knowledge on multiple verification methodology - OVM, UVM. Knowledge on Bus Protocols like AXI, APB and communication protocol like Ethernet Protocol. Familiarity with ARM architecture. Excellent debugging and problem-solving skills.

Enthusiastic VLSI Engineer who stands out through hard work & excellent organization skills. Eager to adapt & utilize my experience, industry standard tools & methodology to deliver high quality solutions for gaining organizational goals as well as enhancing my career in VLSI Domain

A hardworking and passionate job seeker with strong professional skills, willing to work in a challenging environment, with good knowledge of hardware, software, and effective programming skills, and a successful dependable candidate able to manage multiple priorities with a positive attitude and ready to help the team achieve company goals with a willingness to take on additional responsibilities.

Experienced design verification professional with a proven track record in CPU and NoC verification. Successfully developed robust verification environments, implementing advanced methodologies that led to significant coverage improvements and high-quality results. Adept at problem-solving and critical thinking, consistently delivering projects on time and exceeding expectations.

Jiawei Fu

Overview

Work History

Self-Project: AHB Matrix IP Verification

Self-Project: AHB Matrix IP Verification

Self-Project: AHBRAM Verification

Self-Project: MCDF Verification (UVM Structure)

Self-Project: MCDF Verification (SV Structure)

Education

Master of Engineering - Electrical And Computer Engineering

Bachelor of Science - Materials And Nano Sciences

Bachelor of Engineering - Nano Materials And Technologies

Skills

Timeline

Self-Project: AHB Matrix IP Verification

Self-Project: AHB Matrix IP Verification

Self-Project: AHBRAM Verification

Self-Project: MCDF Verification (UVM Structure)

Self-Project: MCDF Verification (SV Structure)

Master of Engineering - Electrical And Computer Engineering

Bachelor of Science - Materials And Nano Sciences

Bachelor of Engineering - Nano Materials And Technologies

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