GOURAV SAINI
Scarborough,Canada
Summary
Dynamic and results-driven professional with 3 years of experience specializing in Synthesis with block size of >2M gates at various lower tech nodes. Responsible for performing static timing analysis (STA), logic equivalence checking (LEC), ECO cycle and Low power techniques, PnR , FloorPlan using Synopsy FC, Innovus, Primetime, and conformality tools. Having Background knowledge in full RTL to GDS cycle
Overview
3
3
years of professional experience
Work History
Synthesis Design Engineer
Qualcomm Canada ULC
05.2022 - Current
- Conducted QDSP block synthesis using Synopsys FC tool, STA using PrimeTime, LEC using Conformality, ECO cycles and Power Optimization
- Successfully completed 3 synthesis tapeouts for DSP blocks based on TSMC 4nm to 2nm tech nodes.
- Spearheading 2nm block PPA activity, including tradeoff analysis between power and performance for optimal tapeout recipes.
- Developed data extraction and mining scripts using Perl/Shell scripting.
- Working closely with Floor Plan and PnR team for better QoR
Education
M.Eng. - Electrical and Computer Engineering
University of Windsor
M.Tech. - VLSI Design
National Institute of Technology (NIT), Kurukshetra
Higher Secondary Education -
D.A.V. Public School
Skills
- Digital logic design principles
- RTL design concepts
- Verilog
- PnR
- Synthesis Flow
- Static Timing Analysis (STA)
- Logic Equivalence Checking (LEC)
- ECO cycle
- Logic synthesis techniques
- Low power estimation
- Timing closure
- Design and Simulation Tools
- Synopsys FC
- PrimeTime
- Conformality
- Xilinx Vivado
- ModelSim
Mooc And Certificates
- VLSI CAD (logic to Layout), Coursera, University of Illinois, 2020
- Digital System: From logic Gates to processors, 06/17
Publications
Unattackable Arduino Data Processing using AES, Accepted and presented at IEEE Conference on Communication and Electronics Systems (ICCES 2019). Collaborated with Dr. R.K. Sharma to implement AES Core interface with Arduino hardware for optimized functionality.
University Projects
- IP Design: AES Core IP (RTL to GDSII), Designed AES Core RTL using Verilog and simulated using Xilinx Vivado., PD flow, synthesis, placement & routing, DRC/LVS error correction using Open EDA tools.
- FPGA RTL Project: MIPS32 5-Stage Pipelined Data Path Design, Created a 5-stage pipelined RISC instruction set architecture data path design in Verilog., Simulated design using Xilinx ISE for functionality verification.
Languages
English
Full Professional
Timeline
Synthesis Design Engineer
Qualcomm Canada ULC
05.2022 - Current
M.Tech. - VLSI Design
National Institute of Technology (NIT), Kurukshetra
Higher Secondary Education -
D.A.V. Public School
M.Eng. - Electrical and Computer Engineering
University of Windsor
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