FNU ZAID MANZOOR KHAN
San Jose
Summary
- Passionate Silicon Implementation Engineer with deep expertise in physical design and methodology development, focused on delivering optimal power, performance, and area (PPA) for next-generation AI accelerators and high-performance compute cores.
- Demonstrated success in taping out complex silicon designs, including AI/HPC-focused chips.
- Hands-on experience with block physical implementation and PPA convergence, from floorplanning to final sign-off.
- Experienced in managing a team of 6+ engineers in physical design, collaborating with RTL designers, and working with EDA vendors and ASIC partners.
Overview
12
12
years of professional experience
Work History
Principal Physical Design Engineer
Apple
Cupertino
03.2022 - Current
- Owned the physical implementation of floorplan blocks from floorplanning to final sign-off for Analog Mixed Signal blocks, like DDR, in next-generation AI accelerators.
- Collaborated with RTL designers to drive optimal block implementation solutions, resulting in PPA-optimized datapath and interconnect solutions
- Developed, built, and owned tools, flows, and methodologies for physical implementation, including the bus router methodology presented at the PD Summit.
- Analyzed and optimized the design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners.
- Noise expert for the AMS team, developing methodologies to prevent EMIR.
- PG template owner for the AMS team, ensuring power estimation and efficiency.
- Worked on custom check balancing of LPDDRs, leveraging physical synthesis, PNR, LEC, and timing closure
- Developed ML skew group method for CTS using Python and TCL to enhance PPA convergence for high-performance compute cores
Silicon Implementation Manager
Cadence Design Systems
San Jose
08.2019 - 02.2022
- Built and led a team of six physical design engineers, developing tools, flows, and methodologies for physical implementation.
- Owned the physical implementation of floorplan blocks for the industry's largest chip, including hands-on experience with top-level design methodologies.
- Obtained a US patent for chip design performance boost, optimizing PPA for AI/HPC-focused chips.
- Reported to the VP of the Palladium Group and collaborated with the main architect for optimal floor planning, placement, CTS, and routing.
- Analyzed and optimized the design for timing, power, and area trade-offs in SoC floor planning.
- Worked with package design teams for bump alignment, and achieved good area saving with the die abutment approach.
- Hands-on experience with block physical implementation and PPA convergence, using strong coding in Python, Bazel, and TCL.
Senior Silicon Implementation Engineer
Qualcomm
San Jose
06.2014 - 07.2019
- Demonstrated success in taping out complex silicon designs, including the first 7nm server chip (HPC-focused), with multi-million gates and various high-speed clocks.
- Owned the physical implementation of floorplan blocks at the chiplet level, from floorplanning to final signoff, including placement, clock tree synthesis, routing, timing closure, physical verification, ECO implementation, and GDS delivery.
- Collaborated with RTL designers to drive optimal block implementation solutions for complex clocking, involving clock mesh, and multi-source CTS to achieve the best PPA.
- Analyzed and optimized the design for timing, power, and area trade-offs in high-performance compute cores.
- Performed RTL synthesis, formal verification (LEC), and STA on complex modules like A53 and A57, leveraging a deep familiarity with industry-standard tools.
- Developed tools and flows for physical implementation, using Python and TCL scripting.
- Performed gate-level simulations in Verdi and Nwave, ensuring physical verification and power estimation.
Education
Master of Science - Electrical, Electronics And Communications Engineering
University of Minnesota Twin Cities
Minneapolis, MN12-2016
Bachelor of Science - Instrumentation Engineering
National Institute of Technology
Trichy05-2014
Skills
- Physical implementation of floorplan blocks from floor planning to final sign-off
- Develop, build, and own tools, flows, and methodologies for physical implementation
- Analyze and optimize design for timing, power, and area trade-offs
- Strong coding experience with Python, Bazel, and TCL
- Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC, and power estimation
- Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification, and timing closure
- Floor plan to GDS expertise, including top-level design methodologies
- Noise champion for AMS, including EMIR prevention
- PG template owner for AMS
- Custom check balancing of LPDDRs
- Cadence tool expertise (Innovus, Virtuoso, etc)
- ML-based CTS skew groups for optimizing PPA in high-performance compute cores
- Hands-on experience with AI or HPC-focused chips
Timeline
Principal Physical Design Engineer
Apple
03.2022 - Current
Silicon Implementation Manager
Cadence Design Systems
08.2019 - 02.2022
Senior Silicon Implementation Engineer
Qualcomm
06.2014 - 07.2019
Master of Science - Electrical, Electronics And Communications Engineering
University of Minnesota Twin Cities
Bachelor of Science - Instrumentation Engineering
National Institute of Technology