Dhwanil Shah
Design Verification And Emulation Manager
San Jose,CA
Summary
- Design Verification and Emulation Lead for 3 Different successful SSD ASIC controllers
- 15+ years of experience in Front-End Verification of IPs, ASICs, FPGAs & SOCs, Emulation and Silicon Validation.
- Emulation experience working for NVIDIA’s GPUs and SSD controller ASICs
- 5+ years of experience working on Palladium, Zebu. Comfortable with Veloce
- Experience working on protocols like LPDDR, PCIe, NVMe, AXI, AMBA, ONFI, I2C, UART, SMBUS
- Experience in developing a thorough test plan, Strong ability to analyze specifications to identify the test scenarios needed to achieve functional testing and coverage goals
- Expert in creating object-oriented, self-checking, reusable test benches for block-level testing and full-chip simulation with constrained-random stimulus and coverage analysis
- Sincere, diligent, meticulous with good understanding of the ASIC and FPGA Design Flow.
- Possess sound Analytical, Quantitative Research and Problem-Solving Skills with rich experience in Verification/Emulation Methodologies.
- Developed tool from scratch for checking RTL Quality without running simulation.
Overview
15
15
years of professional experience
Work History
Design Verification and Emulation Manager
Micron
San Jose, CA
11.2019 - Current
- Responsible for SOC verification , Emulation deliveries ,Silicon Bring up.
- Managed/Lead team of 20 Engineers.
- SOC verification owner for all Tape out related milestones
- Successfully verified and emulated world’s Fastest SSD controller product
- First time silicon success for 4+ ASICs
- Lead for ROM verification on simulation and emulation platforms
- Successful Emulator bring ups for Zebu including PCIe, LPDDR, ONFI and Full chip
- Lead for all Emulation support to FW team.
- Successful silicon Bring up of Full chip, PCIe-gen5, LPDDR and CPUs
- Support entire product development cycle working with FW team.
- Collaborated with cross functional teams like Design managers, Architecture team, Program managers, Firmware teams.
- Innovated new concept tool for checking RTL Quality , Lead 100% development and successfully deployed in live Project
Sr Emulation Engineer
NVIDIA
San Jose, CA
06.2018 - 11.2019
- Created infrastructure to make Billions of gate’s FPGA design emulation friendly.
- Debug FPGA failures on emulation platforms as waves can be dumped, which Saves days of Debug effort on FPGA
- Saved days of FPGA re-work efforts using Emulator runs ahead of FPGA
- Developed full infrastructure of validation for CPU block in leading GPU chip.
- Developed common Initialization Flow for running tests suites
- Run, Maintain 500+ tests validation
- Developed infrastructure to run back2back tests without exiting Emulator and just hitting reset. Saves 5+ Minutes per tests due to that.
Verification and Emulation Lead
PerfectVIPs
11.2012 - 06.2018
- Verification and validation of DDR4 SPIM(serial peripheral interface), DMA (Direct memory access) and protocols using SOC environment
- Responsible on verifying DDR4 based subsystem (Controller + PHY + DRAM) memory.
- Responsible for writing Bring up sequence for DDR4 in UVM and C.
- Developed test bench and required SOC environment components in order to verify DDR subsystem.
- Development of sequences and tests to verify DMA functionality
- Performance analysis
- Verification and validation of Network Ethernet protocols using FPGA board contained Zebu machines (Emulation domain)
- Integration of Transactor based solution on Zebu board for protocols like MAC - 10G,40G,100G and PCS.
- Integration of Transactors with DUT on Zebu board
- Development of C testbench for Transactors.
- Integration/porting of existing UVM/SV testbench on emulation setup
- Development of Ostinato,Spirent based solutions for networking chips verification and validation (GUI + Script)
- Leading the Product delivery Management for MIPI, CSI2/DSI, UFS, & MPHY.
- Managing a team of 12 engineers as well as doing strong technical contribution
- Developed NVMe 1.0b UVM bench and Verification Plan.
- Development of different verification UVM components like Agent, Sequencer, Driver, Monitor and Scoreboard.
ASIC Engineer
Einfochips
08.2010 - 11.2012
- Developed SystemVerilog based verification environment for Gopher FPGA.
- Developed environment components like Agent, Driver, Monitor, & Scoreboard
- Developed VHDL based for Distortion FPGA.
- Developed Test bench Harness concept based environment
Trainee Engineer
SAC ISRO
01.2010 - 05.2010
- Developed Matlab code to create spectrum of available formatted data from Input Ingest Module.
- Verify and analyzed generated spectrum with available spectrum.
Education
Bachelor of Electronics And Communications - Electronic Engineering
Vishwakarma Govt. Engineering College
05.2001 -
Skills
HDL &HVL Languages: UVM, System Verilog, Verilog, System C, UVM, C/ C,
Scripting: Python, Perl, C-shell, & bash
Emulators: Palladium, Zebu, Veloce
Packages/RDA Tools: VCS, Questa, Ncsim, Jira, DO-254 avionics industry standards process
Timeline
Design Verification and Emulation Manager
Micron
11.2019 - Current
Sr Emulation Engineer
NVIDIA
06.2018 - 11.2019
Verification and Emulation Lead
PerfectVIPs
11.2012 - 06.2018
ASIC Engineer
Einfochips
08.2010 - 11.2012
Trainee Engineer
SAC ISRO
01.2010 - 05.2010
Bachelor of Electronics And Communications - Electronic Engineering
Vishwakarma Govt. Engineering College
05.2001 -
Similar Profiles
Kishore Babu JangamKishore Babu Jangam
Data Engineering Manager at MicronData Engineering Manager at Micron
Jing Xiang LimJing Xiang Lim
Senior Financial Analyst at MicronSenior Financial Analyst at Micron
Sisir MohapatraSisir Mohapatra
Director/Site Leader, Managed NAND Engineering at MicronDirector/Site Leader, Managed NAND Engineering at Micron
Bhanu ThumpatiBhanu Thumpati
Firmware Engineer at MicronFirmware Engineer at Micron
Ajith KattilAjith Kattil
Engineering Leader at Neural LabsEngineering Leader at Neural Labs