Avner Kornfeld
San Jose
Summary
Expert in analog, mixed signal, and special circuit designs implemented in state-of-the-art CMOS process technology. Individual contributor and technical mentor employing many years of extensive experience in analog and mixed signal circuit design, innovative analysis methods, characterization, and process technology improvement leadership. Mixed signal IP testing expert, deep knowledge of ADCs, DACs, PLLs, low power biasing sub circuits, and PHY transceiver circuits. CMOS and BJT transistor random and systematic variation expert. Multi-disciplinary problem-solving leader in robust collateral IP circuit design resolving issues arising from new process features. Leader of cross-functional team collaborations to quickly identify root cause for complicated technical road blocks. Architect innovative and non-linear approaches to analysis and solutions. Extensive knowledge of CMOS process and circuit design interaction spanning from 180nm to 7nm technologies. Extensive experience and proven implementation of image sensors. Inventor of 7 patents, author and co-author of more than 15 publications. Core detailed competencies include
Overview
34
34
years of professional experience
Work History
Lead ASIC and System Engineer – R&D
Neuspera Medical Inc.
01.2019 - Current
- Key Company Wide Achievements:
- Identified, and found a technological solution to a major problem and root cause of a system control that caused significant reduction of system performance for some patients and resulted in temporarily halting the second IDE trial. Trial resumed after I addressed the root cause.
- Identified and solved poor wireless transmitter battery charging circuit and fixed optimized the charging scheme. Significantly reduced battery charging field RMA cases.
- Synthesized a novel ‘sacral phantom liquid’ for wireless and implant in a tank for performance characterization. The phantom mimics bodily dielectric properties of the sacral environment at 900 MHz energy transfer band, and also at the much lower stimulation frequency spectrum where the phantom impedance mimics the ~ 1kΩ human figure.
- Found and extensively studied key stimulation maximum distance variables such as radial, axial angles, offset, of the implant relative to its wireless transmitter energy source, impact of electrode array curvature and clocking relative to the implant’s antenna. Performed detailed specialized implant ASIC characterization of energy consumption and its impact on stimulation distance variation. All of these findings were confirmed by an independent technical audit firm.
- Collaborated with cross-functional teams to troubleshoot and resolve technical issues in product development.
Systems HW Engineer
MSEI-BIOTRONIK
01.2018 - 01.2019
- Built analytical modeling of wireless link for implantable medical devices, performing comprehensive analysis of stability, component variation, communication, control, and robust design.
TYFONE INC.
01.2017 - 01.2018
Principal Engineer
INTEL CORPORATION
01.2004 - 01.2016
- LTD-Advanced Design, Hillsboro, OR: Owner and designer of digital temperature sensor circuits (DTS), bandgap and sub-bandgap voltage references, current steering and sigma-delta ADCs. These circuits were released to all product groups as IP collateral of 65nm to 10nm Intel CMOS technologies. Originated analog circuit techniques and transistor stacking to mitigate FINFET analog scaling restrictions. Owner of In-Die Variation (IDV) ring oscillator-based circuits IP for 22 to 7nm FINFET process technology nodes.
- Key Achievements:
- Owned, designed, and productized, digital temperature sensor circuits, bandgap and sub-bandgap references as IP collateral circuits for Intel CPUs and SOCs on 65nm to 10nm CMOS process nodes. Designed current steering and sigma-delta ADCs, linear regulators, Op Amps, current sources, biasing circuits on leading edge technology.
- Originated new IDV frequency / leakage target setting methodology by proper circuit parasitic extraction and accounting for local power delivery effects on resulting oscillation frequency. New methods matches volume data and was approved for all 10nm process / product frequency targets.
- Initiated, implemented, studied, and published first novel results of Random Telegraph Noise (RTN) of single FINFET 14nm transistors extracted from ring oscillators where transistor VT modulation is being observed as oscillation frequency modulation. Results are key in understanding future technology VCCmin and CMOS scaling trends. Paper with state-of-the-art technology was presented at the 2016 VLSI Symposium.
- Developed original methodology to extract MOSFET threshold voltage, VT, from a simple VT ring oscillator circuit. This method used in IDV trending in 22nm to 10nm nodes and applied to major CPUs and SOCs in HVM production. Systematic and random VT distributions were extracted for within dices, wafer level, fab lots, and over long period of production cycles. Trends were used to detect and resolve production issues.
- Extracted high sigma random VT distribution for single fin 14nm was extracted using VT ring oscillators and published in 2015 VLSI Symposium. Study was performed to prove the single fin device has a single, normal distribution, for more than ~ 66 in a single wafer view.
Distinguished Member of the Technical Staff
INTEL CORPORATION
01.1992 - 01.2016
- Designed an analog front end of RFID dielet for the DARPA / Shield counterfeit program. Expanded the design for wireless range increase from 1mm to 15cm by innovative reader and dielet antenna design. Architected a smart card power management integration scheme with more than 25% BOM cost saving, and area saving that can reduce power by 15%.
Senior Staff Component Design Engineer
INTEL CORPORATION
01.1997 - 01.2003
- Mobile Microprocessor Group, Haifa, Israel – Senior member of Intel architecture and design teams that designed the Centrino CPU family. Owned key activities such as power – CPU performance analytical analysis, frequency bin split modeling and target setting for the Banias, Dothan, Yonah, and Merom CPUs. Lead technical direction of the Mobile Microprocessor Group in process features definition setting team responsible to low power process features. Mitigated gate leakage power component by halting gate dielectric thickness scaling when changing from 90nm to 65nm nodes.
- Key Achievements:
- Designed multiple on die bandgap voltage references and temperature sensors. All implemented in HVM silicon.
- Instrumented innovative and detailed power – performance analysis and set post silicon CPU targets, a methodology which is being used at present designs as well, of the Centrino CPUs at 130nm to 45nm technology nodes. Identified, executed, and achieved power reduction efforts of the Centrino CPU family. Proved for the first time that for power constrained CPU, there is an optimum for its FMAX (2000). A major finding to justify architectural changes for single /multi core products.
- Originated and computed pre-silicon total leakage power for Centrino CPUs based on detailed transistor sizing. Achieved good post silicon matching of mean and distribution of total chip leakage (2000-2004). CPU power performance and testing for power binning key patents were granted. Patents 7401241, 7233162, and 7109737.
Staff Component Engineer
INTEL CORPORATION
01.1992 - 01.1996
- Intel Communication Group, Haifa, Israel – Designed the transmitter module of Intel’s 100/10 Mbps Fast Ethernet Transceiver chip used in hundreds of million NIC cards and switches. Originated a novel circuit solution of finite impulse response programmable differential current mode transmitter.
- Key Achievements:
- Redesigned non-robust power delivery & changed power supply pin assignment to combat interference and depressed BER of the first HVM 100 BaseTX/10 BaseT integrated MAC / PHY transceiver. Initiated a new package design with significant supply inductance reduction, subsequent stepping proved the robustness of the new solution. Received “Intel Achievement Award - IAA” for this design robustly manufactured in hundreds million units.
- Designed transmitter circuits that deployed innovative FIR low pass filter for 10Mbps and current mode impedance matching differential current mode with power saving mode for 100Mbps. Implemented an original transmitter design for a Token-Ring PHY IC.
- Originated a new CAT5 equivalent multi-stage RLC filter representing 100 BaseTX electrical cable model that conforms the IEEE 802.3 cable loss versus length specification. This circuit model was crucial in the development of the Intel 82555 innovative receiver circuit.
Education
Doctor of Science - Department of Electrical Engineering
Technion – Israel Institute of Technology
Master of Science - Department of Electrical Engineering
Technion – Israel Institute of Technology
Bachelor of Science - Department of Electrical Engineering
Technion – Israel Institute of Technology
Skills
- Miniaturized neurostimulation devices
- Regulatory testing expertise
- Analog IC Design
- Wireless RFID
- Wireless Implantable Medical Devices
- System HW Design
- Integrated Power Management
- Collateral IP Circuit Design for Low Power Low Voltage CPUs and SOCs
- Interfacing Circuits of Sensors and Silicon
- Device Modeling, E-Test, Circuit Simulation Expertise
- Fast Adopter of New Technologies and Methodologies
- Technical Mentor of Design Teams
- Interdisciplinary Problem Solver
- Extensive Lab and Signal Testing Experience
- Semiconductor device specialist
- VCCmin Low Voltage Design and Process Enablement
- SPICE Models for Device Templates
- Image Sensors
- System engineering
Timeline
Lead ASIC and System Engineer – R&D
Neuspera Medical Inc.
01.2019 - Current
Systems HW Engineer
MSEI-BIOTRONIK
01.2018 - 01.2019
TYFONE INC.
01.2017 - 01.2018
Principal Engineer
INTEL CORPORATION
01.2004 - 01.2016
Senior Staff Component Design Engineer
INTEL CORPORATION
01.1997 - 01.2003
Distinguished Member of the Technical Staff
INTEL CORPORATION
01.1992 - 01.2016
Staff Component Engineer
INTEL CORPORATION
01.1992 - 01.1996
Master of Science - Department of Electrical Engineering
Technion – Israel Institute of Technology
Bachelor of Science - Department of Electrical Engineering
Technion – Israel Institute of Technology
Doctor of Science - Department of Electrical Engineering
Technion – Israel Institute of Technology
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