AVIK SUMED ARUN

Technology: TSMC 5nm
Tools : Synopsis ICC2, Synopsis PrimeTime.
Roles & Responsibility :

• Timing Analysis at Full Chip level and providing tile level feedback.
• Interface timing analysis and closure at the Full-Chip Level.
• Full Chip Level Special Timing Checks and Timing Closure.
• 2-Tile Interface Timing Closure.

Technology: TSMC 5nm

Tools : Synopsis ICC2, Synopsis PrimeTime.

Roles & Responsibility :

• Various FloorPlan experiments at Full Chip Level.
• Robust Pin Planning at Full Chip Level.
• Insertion of Feedthrus.
• PnR at Full Chip Level.
• Full Chip Level Timing Closure.

Technology: TSMC 5nm

Tools : Synopsis ICC2, Fusion Compiler, PT, Calibre.

Roles & Responsibility :

• Handling of various Blocks through PnR Flow, and achieving Target QOR.
• Various FP experimentation and providing feedback to FCFP team and respective tile owners.
• Involved in Improvement of 5nm PnR flow for faster PnR runtime, and providing feedback. Achieved reduction of 3 days for blocks above 3 million instances.
• Involved in Flow improvement w.r.t to over all QOR and DRC improvement and providing feedback.
• Full Chip Floorplanning. Signal Pins/Ports and Feedthru insertion.
  

Technology : TSMC 7nm

Tools : Synopsis ICC2, PT, Calibre.

Roles & Responsibility :

• Responsible for handling two blocks and implementation. Floorplanning, Placement, CTS and Routing.
• Responsible for ECO, Timing Closure and Physical Verification and IR/EM fixes.
  

Technology : TSMC 7nm

Tools : Synopsis ICC2, PT, Calibre.

Roles & Responsibility :

• Responsible for handling two blocks and implementation. Floorplanning, Placement, CTS and Routing.
• Responsible for ECO, Timing Closure and Physical Verification and IR/EM fixes.