AVIK SUMED ARUN
Highly motivated Physical Design Engineer with over 6 years of experience in Block-level Physical Design (Netlist to GDSII) and expertise in TSMC 7nm & 5nm technology nodes. Proficient in Timing Closure, ECO Cycle PV, Full Chip Static Timing Analysis, Special Timing Checks, Floorplanning, Pin-placement, Manual Feedthru insertion, and Full-Chip-Level PnR. Currently focused on Full Chip Static Timing Analysis and Timing Closure. Seeking a challenging role to further refine skills and contribute as a valuable asset to an organization. Known for a proactive and creative approach to problem-solving, eager to leverage expertise and dedication to drive progress in chip design. Adaptable to evolving technological landscapes and committed to delivering high-quality results.
Work History
LEAD ENGINEER - PHYSICAL DESIGN
3 Years 6 MonthsTechnology: TSMC 5nm
Tools : Synopsis ICC2, Synopsis PrimeTime.
Roles & Responsibility :
- Timing Analysis at Full Chip level and providing tile level feedback.
- Interface timing analysis and closure at the Full-Chip Level.
- Full Chip Level Special Timing Checks and Timing Closure.
- 2-Tile Interface Timing Closure.
LEAD ENGINEER - PHYSICAL DESIGN
1 Year 3 MonthsTechnology: TSMC 5nm
Tools : Synopsis ICC2, Synopsis PrimeTime.
Roles & Responsibility :
- Various FloorPlan experiments at Full Chip Level.
- Robust Pin Planning at Full Chip Level.
- Insertion of Feedthrus.
- PnR at Full Chip Level.
- Full Chip Level Timing Closure.
Sr.Physical Design Engineer, Team Lead
2 Years 1 MonthTechnology: TSMC 5nm
Tools : Synopsis ICC2, Fusion Compiler, PT, Calibre.
Roles & Responsibility :
- Handling of various Blocks through PnR Flow, and achieving Target QOR.
- Various FP experimentation and providing feedback to FCFP team and respective tile owners.
- Involved in Improvement of 5nm PnR flow for faster PnR runtime, and providing feedback. Achieved reduction of 3 days for blocks above 3 million instances.
- Involved in Flow improvement w.r.t to over all QOR and DRC improvement and providing feedback.
- Full Chip Floorplanning. Signal Pins/Ports and Feedthru insertion.
Physical Design Engineer
10 MonthsTechnology : TSMC 7nm
Tools : Synopsis ICC2, PT, Calibre.
Roles & Responsibility :
- Responsible for handling two blocks and implementation. Floorplanning, Placement, CTS and Routing.
- Responsible for ECO, Timing Closure and Physical Verification and IR/EM fixes.
Physical Design Engineer
1 Year 1 MonthTechnology : TSMC 7nm
Tools : Synopsis ICC2, PT, Calibre.
Roles & Responsibility :
- Responsible for handling two blocks and implementation. Floorplanning, Placement, CTS and Routing.
- Responsible for ECO, Timing Closure and Physical Verification and IR/EM fixes.