Arti Ahuja
Santa Clara,CA
Summary
Senior product and program leader with 25+ years across server platforms, AI systems, manufacturing support, diagnostics, and validation. Known for owning complex programs end to end, integrating plans across large cross-functional teams, and translating technical ambiguity into clear execution, risk, and deployment decisions. Recent work spans end-to-end ownership of BiDi BERT from conceptualization through deployment planning — including manufacturing plan of record, capacity, and supply-chain coordination — leadership of the OneDiag PRR / NVLIT and NVL5 / NVL6 diagnostic programs, and Kyber Blackwell bring-up and manufacturing readiness. Influences and aligns teams without formal authority and keeps leadership equipped to decide on readiness, scale, and deployment.
Overview
20
20
years of professional experience
Work History
Product / Project Program Manager, Data Center Systems
NVIDIA
Santa Clara, CA
01.2024 - Current
- Product Program Manager for BiDi BERT — owned the program end to end from conceptualization through deployment planning across NVIDIA teams, factory partners, and external suppliers. Integrated manufacturing plan of record (POR), capacity strategy, supply-chain coordination, build planning, and risk management as the overall-view integrator across organizations numbering in the hundreds.
- Project Program Manager for the OneDiag PRR, NVLIT, NVL5, and NVL6 diagnostic programs — integrated engineering, operations, validation, firmware, and customer-facing workstreams to advance release readiness, diagnostic enablement, and customer qualification across 50+ teams.
- Led EB1/EB2 Kyber Blackwell compute-tray bring-up from first power-on through stable L6/L10/L11 mini-rack readiness as primary execution and validation lead, and initiated the Kyber power-testing strategy that enabled B0C0 DC side-car testing — coordinating NVIDIA validation, FW/SW, mechanical, and thermal teams with SMC/JDM partners and external vendors.
- Defined and led the L10 build process at SMC and L10 validation at Toyama — authoring the workflows, setup guides, recipes, toolkits, provisioning paths, and trackers used by both NVIDIA and SMC — and stood up the Toyama Kyber lab, restoring operations in under 12 hours after a safety shutdown.
- Reduced the L10 bonepile from several hundred units to fewer than 20 by investigating 50+ manufacturing error signatures and recovering units that would otherwise have been scrapped, protecting manufacturing continuity and quality.
- Delivered 33+ TS3 units ahead of schedule against an original ask of 25, partnering across IGS, NV Operations, NV Diagnostics, Thermal, Mechanical, and Engineering to meet aggressive demand.
- Ran key cross-functional forums — power-strategy reviews, daily bring-up huddles, NV–SMC discussions, and NVLink debug meetings — and produced reports, trackers, and status updates repeatedly recognized by stakeholders for clarity and timeliness.
Senior Hardware Engineer
Microsoft Corporation
Redmond, WA
01.2015 - 01.2024
- Led validation and release of multiple server SKUs and AI-based server systems for Microsoft data centers — creating system requirements, verification and operations guides, test plans, and test cases, and establishing a monthly validation regression process.
- Built end-to-end processes for system setup, test execution, bug filing, and reporting, and drove rapid issue resolution across BIOS, BMC, OS, driver, FPGA, SoC, Cerberus, network adapter, switch, and ToR teams.
- Partnered with internal and external engineering teams — Mellanox, Intel, ZT Systems, Lenovo, Quanta, and Wiwynn — and trained 100+ engineers to increase capacity and parallel platform development.
Software Development Engineer II
Microsoft Corporation
Redmond, WA
01.2012 - 01.2015
- Improved cloud-system scalability, resiliency, and defect identification through architecture analysis, tool development, automation, and rigorous testing.
Component Design Engineer (Grade 6/7)
Intel Corporation
Santa Clara, CA
01.2006 - 01.2012
- Led validation and tool enhancement across the Jaketown, Tylersburg, and Beckridge server chipsets, discovering 36+ RTL bugs in critical high-speed components and earning multiple awards.
- Promoted to Grade 7 for leading the Array DFT validation team, resolving issues beyond assigned scope, and acting as a consultant across 8 engineering teams.
- Developed scalable validation and automation approaches that avoided full test rewrites, supported 25+ engineers, and helped resolve 250+ issues under tight schedules.
Education
Bachelor of Engineering - Electronics & Telecommunications
University of Pune
IndiaPCIe Gen 3 -
Mindshare
UVM Adopter And System Verilog -
Doulos
Skills
- Smartsheet Scheduling
- Build planning
- Capacity Planning
- Data collection & research
- NVLink
- PCIe
- DFT
- EV / DV / PV validation
- Cross-functional coordination
- Team leadership and direction
- Critical thinking
- Verbal and written communication
- Relationship building
- Risk & issue management
- Vendor management
AWARDS & RECOGNITION
Unsung Hero Award — Microsoft Corporation, Department Award for Tool Development and multiple Spontaneous Recognition Awards — Intel Corporation
EARLIER EXPERIENCE
- Design Associate — Pegasus Technologies, Inc., Lenoir City, TN (2005–2006)
- Senior Engineer / Development Engineer — NitAI Computer Systems Pvt. Ltd., Pune, India (2000–2004)
Timeline
Product / Project Program Manager, Data Center Systems
NVIDIA
01.2024 - Current
Senior Hardware Engineer
Microsoft Corporation
01.2015 - 01.2024
Software Development Engineer II
Microsoft Corporation
01.2012 - 01.2015
Component Design Engineer (Grade 6/7)
Intel Corporation
01.2006 - 01.2012
Bachelor of Engineering - Electronics & Telecommunications
University of Pune
PCIe Gen 3 -
Mindshare
UVM Adopter And System Verilog -
Doulos