Andrew Lee
Los Angeles
Summary
Dynamic Electrical Engineer specializing in hardware security and innovative nonvolatile memory design, with expertise in In/Near-memory computing. Proven track record of successful tape-out projects, demonstrating a commitment to excellence in engineering practices. Cross-disciplinary experience in medical device design, particularly in neuromodulation, immunomodulation, and neuromuscular stimulation, alongside a strong interest in advancing exosome research. Committed to leveraging engineering skills to drive impactful solutions in technology and healthcare sectors.
Overview
5
5
years of professional experience
Work History
Graduate Research Assistant
UCLA
Los Angeles, CA
09.2025 - Current
- Engineered Maintained printed circuit boards in laboratory environment. optimization for 32-channel stimulation and 128-channel recording in bidirectional neuromodulation devices.
- Developed project proposals to explore advancements in neuromodulation and general bio-modulation fields, including immunomodulation, exosome production, vagus nerve stimulation, and neuromuscular stimulation.
- Developed and implemented innovative cell culture experiment designs and electrical stimulation protocols
Visiting Graduate Researcher
UCLA
Los Angeles, CA
12.2024 - 08.2025
- Engineered iOS/macOS applications for integration with a 32-channel stimulation and 128-channel recording bidirectional neuromodulation device.
- Assisted with chip bonding and soldering. Collected and analyzed compound action potential data from invasive animal experiments.
- Developed AI-driven prognostic tool for predicting amyloid-beta plaque accumulation in Alzheimer's disease.
Teaching Assistant
NTHU
09.2023 - 01.2024
- Introduction to Integrated Circuit Design (EE32300)
- Facilitated office hours, supported class projects, and graded assignments to enhance student understanding of integrated circuit design concepts.
- Full custom design 128 x 16 ROM Macro
- Mentored students on final projects, providing guidance and feedback to foster design skills and project execution.
- Designed and implemented a full custom 128 x 16 ROM macro, demonstrating proficiency in digital design and circuit functionality.
Intern
TSMC, Advanced Memory Design and Technology, AMDT
07.2023 - 09.2023
- Reviewed SRAM architecture and analyzed macro-level power integrity to ensure design reliability
- Assisted in developing advanced memory design processes and methodologies.
- Conducted testing on memory devices to ensure compliance with quality standards.
- Collaborated with engineering teams to troubleshoot design challenges and improve performance.
Research Assistant
NTHU
09.2022 - 05.2025
- Contributed to MRAM team efforts in developing near memory computing and security solutions.
- Developed near-memory computing solutions for AI edge devices, optimizing performance for common neural networks, including MobileNetV2, Bayesian NN, and MobileViT.
- Designed a novel MRAM write operation scheme to enhance data storage efficiency.
- Participated in DRAM team initiatives focused on memory technology advancements.
- Collaborated with Nanya Tech on DRAM sense amplifier simulations and conducted in-depth analysis of process variations and biases, focusing on metrics like min Ccell, power, and delay.
- Prof. Meng-Fan Marvin Chang
Intern
PUFsecurity, subsidiary of eMemory
07.2021 - 09.2021
- Conducted Side-Channel Attack (SCA) vulnerability analysis to identify security weaknesses in systems
- Developed circuit for detecting power SCA vulnerabilities
- Assisted in design verification processes for advanced memory technologies.
- Supported the development and testing of memory architecture in collaborative team environment.
- Conducted data analysis to identify trends in memory performance metrics.
Education
Ph.D. - Bioengineering
University of California, Los Angeles
Los Angeles, CA08-2029
Master of Science - Electrical Engineering
Institute of Electronic Engineering, NTHU
HsinChu, Taiwan05-2025
B.S. - Electrical Engineering and Computer Science
Electrical Engineering & Computer Science, NTHU
HsinChu, Taiwan01-2022
Skills
- Complete proficiency of the entire design flow from design to measurement
- Digital design : Verilog
- Simulation : Virtuoso, Hspice, LTspice
- Custom layout : Laker, virtuoso, Calibre DRC/LVS/PEX
- Board Integration: EasyEDA (PCB), Matlab Simulink (Microcontroller)
- Measurement equipment : Function Generator, Data Generator, Logic Analyzer, Oscilloscope, FPGA
- Matlab, Python, Perl
- General cell culture, qPCR, NTA
- Native Speaker in Chinese and English
Affiliations
- Graduate Student Researcher in Biomimetic Research Lab (BRL), UCLA 2025-Now
- General Manager in Memory Design Lab (iMDL), NTHU 2023-2025
- EECS student union manager, NTHU 2021-2022
Timeline
Graduate Research Assistant
UCLA
09.2025 - Current
Visiting Graduate Researcher
UCLA
12.2024 - 08.2025
Teaching Assistant
NTHU
09.2023 - 01.2024
Intern
TSMC, Advanced Memory Design and Technology, AMDT
07.2023 - 09.2023
Research Assistant
NTHU
09.2022 - 05.2025
Intern
PUFsecurity, subsidiary of eMemory
07.2021 - 09.2021
B.S. - Electrical Engineering and Computer Science
Electrical Engineering & Computer Science, NTHU
Ph.D. - Bioengineering
University of California, Los Angeles
Master of Science - Electrical Engineering
Institute of Electronic Engineering, NTHU
Honors and Awards
- Foreign exchange scholarship NTHU, 2022, University of Minnesota (UMN)
- Summer exchange scholarship NTHU, 2019, Tsinghua University (THU)
- Distinguished freshman scholarship NTHU, 2018
Publications
- A 22nm nonvolatile AI-edge processor with 21.4 TFLOPS/W using 47.25 Mb lossless-compressed-computing STT-MRAM near-memory-compute macro 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
- A 22nm 104.5 TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks 2025 IEEE International Solid-State Circuits Conference (ISSCC)
- A 22nm 8Mb STT-MRAM near-memory-computing macro with 8b-precision and 46.4-160.1 TOPS/W for edge-AI devices 2023 IEEE International Solid-State Circuits Conference (ISSCC)
- A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks IEEE Journal of Solid-State Circuits
- A Nonvolatile AI-Edge Processor With Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro Using Dynamic Floating-/Fixed-Point Accumulation IEEE Journal of Solid-State Circuits