Amol Mathur
Folsom
Summary
Experienced in merging ASIC technology with business requirements to address evolving challenges and resolve a wide range of issues. Possesses skills and expertise necessary to excel as a technical leader. Over 20 years of experience in the ASIC development life cycle. Well-prepared to embrace a new opportunity that offers long-term potential and ample room for professional advancement.
Overview
21
21
years of professional experience
Work History
Director, AI Silicon Design
Microsoft
02.2025 - Current
- Leading team of 20 engineers to deliver Customized NOC Fabric to SOC for Microsoft's Azure AI accelerator.
- Driving Planning and Execution of Micro Architecture development , RTL design , DV & SOC integration with in-house and third party vendor teams with desired key performance Indicators.
Technical Lead/Manager, Camera IP
Google
09.2022 - 02.2025
- Leading team of 24 engineers across various time zones, to deliver state of the art camera IP to SOC for Google's pixel phone. Responsible for Planning and execution involving third party vendor IP collaboration, in-house IP development , catering to DFT, PD, SOC, DV, Emulation, Post Silicon and software teams.
- Closely works with Product, Power and system architecture team to implement and enable features in silicon with best PPA metric.
- Mentoring and coaching team members
Technical Lead/Manager, GPU Power Subsystem
Intel
09.2015 - 09.2022
- Lead and managed team of 10 engineers to deliver Power management subsystem to Intel's discrete and integrated graphics products.
- Responsible for power management subsystem development , DV closure and post silicon enabling. Enabled various flag ship power management features in GPU and delivered various execution efficiency improvement ideas to bring down IP development cycle.
Design Manager
Synaptics Inc
04.2013 - 09.2015
- Technically lead and managed team of 8 Engineers to develop and integrate touch-sensing IP to the SOC for Samsung's phone.
- Responsible for planning and execution of RTL development and DV closure working contract workers based in India.
Senior Design Engineer, GPU
Intel
07.2006 - 04.2013
- Responsible for developing RTL for GPU's I-cache , multi threaded Execution units, working with DV team to achieve DV quality and served as point-of-contact for Silicon debugs.
Design Engineer, FPGA
Telsima (start up co.)
08.2004 - 07.2006
- Responsible for RTL development and implementation in FPGA to communicate with HOST processor to perform voice compression on E1 lines.
Education
Master of Science - Microelectronics
Birla Institute of Technology And Science (BITS)
06-2010
Skills
- Team leadership
- Project management
- Low power Design
- Verilog/System-Verilog
- Well verse with ASIC Design life cycle, RTL , UPF, VCLP, STA, CDC, RDC, Power estimation tools, Floor planning , DV , DFT, DFM
- Experience with GPU Architecture, Camera Architecture, AMBA protocols, NOC/Fabric, AI/ML accelerators, Post Si debug capabilities,
- Experience with scalable implementation of IP catering to multiple market segments
- Experience working with Third party vendor Design/DV team, buy vs make, SIP vs HIP
Accomplishments
- Peer Bonus Award at Google
- Department recognition awards (DRA) at Intel
- Paper published in DTTC (Intel wide conference)
Timeline
Director, AI Silicon Design
Microsoft
02.2025 - Current
Technical Lead/Manager, Camera IP
Google
09.2022 - 02.2025
Technical Lead/Manager, GPU Power Subsystem
Intel
09.2015 - 09.2022
Design Manager
Synaptics Inc
04.2013 - 09.2015
Senior Design Engineer, GPU
Intel
07.2006 - 04.2013
Design Engineer, FPGA
Telsima (start up co.)
08.2004 - 07.2006
Master of Science - Microelectronics
Birla Institute of Technology And Science (BITS)