Abinaya Chinnusamy
661 Thompson avenue,BC
Summary
Analytical FPGA Design Engineer focused on applying sound engineering principles using both traditional and innovative methods.
Overview
6
6
years of professional experience
1
1
Certification
Work History
FPGA Design Engineer
Epson Canada
05.2023 - 08.2023
- Designed SPI protocol using hardware description languages such as Verilog to architect RTL designs for efficient and optimized performance in XILINX-VIVADO.
- Conducted thorough testing to validate RTL designs against specifications and requirements.
- Streamlined synthesis design constraints and resolved STA issues as well as gate-level simulation failures.
- Addressed design challenges and evaluated alternative design scripts to meet project requirements.
- Liaised with stakeholders to define and document design requirements.
RTL Design Engineer
Ignitarium Technology Solutions
01.2021 - 10.2022
- IP integration, lint and CDC closure to ensure quality of design.
- Developed and implemented scripts to automate Jasper Gold CDC and Lint.
- Presented technical findings and recommendation to improve design quality by conducting detailed reviews, analyzing violations and implementing necessary changes.
- Collaborated with Product owners to define customization requirements .
- Drafted Micro-Architectural documents for peripherals such as UART, I2C and SPI detailing design requirements and technical specifications.
Graduate Student Intern
Robert Bosch Engineering And Business Solutions
07.2019 - 06.2020
- Assisted Lead Engineers in preparing specification documents, resulting in more efficient design models.
- Gained valuable experience working closely with experienced professionals on various "Software As Product" (SWAP).
- Contributed to successful completion of research projects through diligent data collection, organization, and interpretation of different design methodologies (Electronic Stability Program (ESP) and AUTOSAR software Architecture.)
- Collaborated with team members to develop strategies to increase prototype integrity.
Student Research Assistant
Signal Processing Lab, KEC
12.2017 - 04.2018
- Maintained up-to-date records of research activities and results for future reference.
- Facilitated communication between researchers and faculty members by regularly updating progress reports and sharing key findings.
- Conducted thorough experiments following established protocols while accurately documenting results for future reference.
- Improved data quality by meticulously reviewing and cleaning datasets before analysis.
- Performed statistical, qualitative, and quantitative analysis.
Education
Masters of Engineering - VLSI Design Engineering
PSG College of Technology
India09.2020
Bachelors of Engineering - Electronics And Communications Engineering
Kongu Engineering College
India04.2018
Skills
- HDL: Verilog, System Verilog
- Programming Language: C,C,Python
- Protocols: UART,SPI,APB,AHB
- Cadence - Jaspergold CDC and Lint
- Xilinx - Vivado
- Mentorgraphics - Questa Sim
Certification
Xilinx Alliance Certification - Ignitarium Technology Solutions
JAN 2021 - MAY 2021
Training included Designing FPGA’s using Vivado Design Suite
Timeline
FPGA Design Engineer
Epson Canada
05.2023 - 08.2023
RTL Design Engineer
Ignitarium Technology Solutions
01.2021 - 10.2022
Graduate Student Intern
Robert Bosch Engineering And Business Solutions
07.2019 - 06.2020
Student Research Assistant
Signal Processing Lab, KEC
12.2017 - 04.2018
Masters of Engineering - VLSI Design Engineering
PSG College of Technology
Bachelors of Engineering - Electronics And Communications Engineering
Kongu Engineering College
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